Nxp B.v.

Rick Varney

Ata Khan

Craig A MacKenna

Gregory Goodhue

Pankaj Shrivastava

Greg Goodhue

Prithvi Nagaraj

Bas Van Der Veer

A microcontroller using an optimized buffer replacement strategy comprises a memory configured to store instructions, a processor configured to execute said program instructions, and a memory accelerator operatively coupled between the processor and the memory. The memory accelerator is configured to receive an information request and overwrite the buffer from which the prefetch was initiated with the requested information when the request is fulfilled by a previously initiated prefetch operation.

Memory accelerator buffer replacement method and system

One embodiment of the present application includes a microcontroller () that has an embedded memory (), a programmable processor (), and a test interface (). The memory () is accessible through the test interface (). In response to resetting this microcontroller (), a counter is started and the test interface () is initially set to a disabled state while an initiation program is executed. The test interface () is changed to an enabled state&#x2014;such that access to the embedded memory () is permitted through it&#x2014;when the counter reaches a predefined value unless the microcontroller () executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller () operation.

Embedded memory protection

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Campbell, CA, United States of America

Rick Varney