Nvidia Corporation

Rick M Iwamoto

Curtis R Priem

Franck Diard

Stephen P Johnson

David G Reed

David S Rosenthal

Brian D Hutsell

A system and method for remapping and redirecting accesses to a memory space shared between graphics devices permits a single device driver to interface between an application program and multiple graphics devices. Each graphics device provides configuration information to the BIOS (basic input/output system), particularly memory space requirements for prefetchable and non-prefetchable memory spaces. A memory space allocation for the graphics devices is determined based on the configuration information. A switch device, interfacing between a host processor and each graphics device, is programmed to redirect accesses to a portion of the allocated memory space to only one of the graphics devices. Accesses to another portion of the allocated memory space may be remapped to all of the graphics devices or a subset of the graphics devices.

Broadcast aperture remapping for multiple graphics adapters

A system and method for representing multiple prefetchable memory resources, such as frame buffers coupled to graphics devices, as a unified prefetchable memory space for access by a software application. A graphics surface may be processed by multiple graphics devices, with portions of the surface residing in separate frame buffers, each frame buffer coupled to one of the multiple graphics devices. One or more redirection regions may be specified within the unified prefetchable memory space. Accesses within a redirection region are transmitted to a prefetchable memory of a single graphics device. Accesses within the unified prefetchable memory space, but outside of any redirection region may be broadcast to all of the prefetchable memories of the multiple graphics devices.

Frame buffer region redirection for multiple graphics adapters

Systems and methods for private addressing in a multi-processor graphics processing subsystem having a number of memories and a number of graphics processors. Each of the memories includes a number of addressable storage locations, and storage locations in different memories may share a common global address. Storage locations are uniquely identifiable by private addresses internal to the graphics processing subsystem. One of the graphics processors is able to access a location in a particular memory by referencing its private address.

Private addressing in a multi-processor graphics processing system

A process of coordinating access to a shared resource by a plurality of execution units is provided. Channel control units are used to coordinate access to a shared resource. Each channel control unit reads semaphore values of a semaphore storage unit. In response to synchronization commands and semaphore values, the channel control unit manages the flow of execution instructions to the execution units in order to manage access to the shared resource.

Semaphore enhancement to improve system performance

A direct memory access (DMA) circuit which is physically positioned with an input/output device, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of system memory in which data is stored for transfer to the I/O device, a value determining a position within the buffer portion of system memory beginning at which a next sequence of data is to be placed, and a value determining a position within the buffer portion of system memory from which a next sequences of data is to be copied to the I/O device, the DMA circuit including circuitry for reading data from the buffer portion of system memory beginning at the position from which a next sequences of data is to be copied and for writing the data read to the I/O device.

Apparatus for accelerating the rendering of images

An integrated circuit including a plurality of connectors for communicating with circuitry within the integrated circuit, a plurality of input/output pads for connecting to external circuitry, a plurality of multiplexors joined to the connectors and the input/output pads, means for providing an external control signal for each multiplexor for joining the plurality of connectors for communicating with circuitry within the integrated circuit to correct input/output pads for connecting to external circuitry for operating the integrated circuit.

Multiuse input/output connector arrangement for graphics accelerator integrated circuit

Method and apparatus for accelerating the rendering of images

A direct memory access (DMA) arrangement having a DMA circuit which is positioned with an input/output device, the DMA circuit including a first register for storing a reference value pointing to a first data structure established by an application program which includes details of a transfer buffer in memory in which data is stored for transfer to the I/O device, two additional registers for storing an address and a range at which the data is stored within the transfer buffer in memory, and a fourth register for storing a reference value pointing to a second data structure which includes details describing a notification area of memory at which a notification from the DMA circuit that a transfer of data has been completed may be stored.

Growing community of inventors

Cupertino, CA, United States of America

Rick M Iwamoto