Texas Instruments Corporation

Other

Rick L Wise

Angelo Pinto

Hiroaki Niimi

Manoj Mehrotra

Weize W Xiong

Cloves Rinn Cleavelin

Mark Stephen Rodder

Darius Lammont Crenshaw

Katherine E Violette

Charles Frank Machala, Iii

Aditi D Banerjee

Hiroshi Yasuda

Sameer P Pendharkar

Amitava Chatterjee

Mahalingam Nandakumar

Jiong-Ping Lu

Amitabh Jain

Douglas Ticknor Grider

Ricky A Jackson

Rajesh B Khamankar

Jeffrey A McKee

Francis Gabriel Celii

Stuart M Jacobsen

Naveen Tipirneni

William F Richardson

Nicholas Stephen Dellas

Ih-Chin Chen

Vladimir Frank Drobny

Periannan Chidambaram

Bradley David Sucher

Puneet Kohli

Django Trombley

Stanton Petree Ashburn

Douglas E Mercer

Sreenath Unnikrishnan

Maureen A Hanratty

Phillipp Steinmann

Maria Wang

Chih-Ping Chao

Johan Weijtmans

Michael A Kasner

A folding camper has a body having a lower end configured for positioning within a bed of a pickup truck or on a trailer. The camper has sidewalls rotationally engaged between the roof and body whereby the folding camper is moveable between a collapsed position wherein a first sidewall and a second sidewall and a front wall and rear wall are all folded to a substantially horizontal positioning, to a deployed positioning wherein the roof is elevated above an upper end of the body with the first sidewall and the second sidewall both rotated to a substantially vertical positioning.

Folding camping apparatus

An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

High mobility transistors

An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1&#xb7;10atoms/cm, and an emitter-base junction less than 40 nanometers deep in a base layer. A process of forming the bipolar transistor, which includes forming an emitter dopant atom layer between a base layer and an emitter layer, followed by a flash or laser anneal step to diffuse dopant atoms from the emitter dopant atom layer into the base layer.

Ultrashallow emitter formation using ALD and high temperature short time annealing

The dominant frequency of a solidly mounted resonator () is substantially increased by reducing the thickness of each layer of each Bragg acoustic reflector () to have a thickness than is substantially equal to one-quarter of the wavelength of a frequency that is a higher harmonic resonant frequency of the fundamental resonant frequency of the solidly mounted resonator ().

Temperature compensated bulk acoustic wave resonator with a high coupling coefficient

An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

An integrated silicon and III-N semiconductor device may be formed by growing III-N semiconductor material on a first silicon substrate having a first orientation. A second silicon substrate with a second, different, orientation has a release layer between a silicon device film and a carrier wafer. The silicon device film is attached to the III-N semiconductor material while the silicon device film is connected to the carrier wafer through the release layer. The carrier wafer is subsequently removed from the silicon device film. A first plurality of components is formed in and/or on the silicon device film. A second plurality of components is formed in and/or on III-N semiconductor material in the exposed region. In an alternate process, a dielectric interlayer may be disposed between the silicon device film and the III-N semiconductor material in the integrated silicon and III-N semiconductor device.

Layer transfer of silicon onto III-nitride material for heterogenous integration

An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orienations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0&#xb0; or 90&#xb0; rotations.

Integrated circuits with aligned (100) NMOS and (110) PMOS finFET sidewall channels

An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0&#xb0; or 90&#xb0; rotations.

Integrated circuits with aligned (100) NMOS and (110) PMOS FinFET sidewall channels

A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

Reduction of STI corner defects during SPE in semiconductor device fabrication using DSB substrate and hot technology

A method for forming epitaxial SiGe of a PMOS transistor. In an example embodiment, the method may include providing a semiconductor wafer having a PMOS transistor gate stack, extension sidewalls, source/drain extension regions, and active regions. The method may also include performing a recess etch of the active regions and forming epitaxial SiGe within the recessed active regions by forming a selective epi SiGe region coupled to the surface of the recessed active regions and a selective carbon-doped epitaxial cap layer coupled to the selective epi SiGe region.

Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial SiGe

A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800&#xb0; C. and 1300&#xb0; C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800&#xb0; C. and 1250&#xb0; C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (&#x2267;) 5.5&#xb0; C./min.

Accelerated furnace ramp rates for reduced slip

Growing community of inventors

Fairview, TX, United States of America

Rick L Wise