Intel Corporation

Rick Coulson

Knut Stener Grimsrud

Robert W Faber

Sanjeev N Trika

John I Garney

Robert J Royer, Jr

Bruce A Young

Frank T Hady

Brian Dees

David GenLong Chow

Mason B Cabot

Jeanna N Matthews

Anthony S Bock

Embodiments of methods to communicate a timestamp to a storage system are generally described herein. Other embodiments may be described and claimed.

Methods to communicate a timestamp to a storage system

Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.

NAND power fail recovery

A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

Technique to write to a non-volatile memory

One aspect of the invention provides a novel scheme to preserve the failure state of a memory location. According to one embodiment, the data is read from a memory location in a read-destructive memory device. If the data is found to be valid (uncorrupted) it is written back to the memory location from where it was read in order to preserve it. If the data is found to be invalid (corrupted) then a failure codeword is written in the memory location to indicate a failure of the memory location. The failure codeword may be preselected or dynamically calculated so that it has a mathematical distance greater than all correctable data patterns.

Method and apparatus for preservation of failure state in a read destructive memory

An integrated circuit includes a trace analyzer to sample, process and store data carried along internal or external data path of the circuit. The trace analyzer may include a multiplexer, a sampler, a formatter and a memory controller. The trace analyzer samples data on a predetermined basis, processes it and caused the processed data to be stored in a memory.

Integrated circuit with trace analyzer

Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.

Stacked memory device having shared bitlines and method of making the same

An apparatus is equipped with a disk block allocation optimization function for generating, if possible, an alternative disk block allocation for a current disk block allocation that will yield improved overall access time for a sequence of file accesses. The function includes logic for tracing the sequence of logical file accesses, then mapping the traced logical file accesses to physical disk blocks to determine the current disk block allocation, logic for generating the alternative disk block allocation, if possible, using the physical trace results, and logic for effectuating the alternate disk block allocation, if generated. In one particular embodiment, the logic for generating the alternative disk block allocation employs a random search approach, while in another embodiment, the logic for generating the alternative disk block allocation employs a heuristic approach.

Disk block allocation optimization methodology and application

A method and system are disclosed for measuring simultaneously and at randomly distributed intervals throughputs sets on one or more busses under test and displaying the percent occurrences of those throughputs sets in a graph as a density function. A method and system are also disclosed for simultaneously measuring throughput sets on one or more busses under test given that user specified stimuli are input into those busses and displaying those throughput sets in a graph as concurrency plots.

Method and system for simultaneously displaying the throughput on multiple busses

A computer system is equipped with an operating system having a tracer driver for generating trace data including disk locations accessed for disk accesses made by various components of the operating system during system startup/boot time. The tracer driver is loaded at an initial phase of system start-up. The computer system is further equipped with a companion disk block relocation driver for generating, if possible, an alternative disk block allocation for a current disk block allocation that will yield improved overall access time for a sequence of disk accesses. In some embodiments, the disk block relocation driver includes logic for tracing the sequence of disk accesses to determine the current disk block allocation, logic for generating the alternative disk block allocation, if possible, using the trace results, and logic for effectuating the alternate disk block allocation, if generated. In one particular embodiment, the logic for generating the alternative disk block allocation employs a random search approach, while in another embodiment, the logic for generating the alternative disk block allocation employs a heuristic approach.

Reducing operating system start-up/boot time through disk block

A computer system is programmed with a plurality of programming instructions for implementing a software function, having an installation utility with logic for generating, if possible, an alternative disk block allocation for a current disk block allocation that will yield improved overall access time for a sequence of disk accesses. In some embodiments, the logic includes logic for tracing the sequence of disk accesses to determine the current disk block allocation, logic for generating the alternative disk block allocation, if possible, using the trace results, and logic for effectuating the alternate disk block allocation, if generated. In one particular embodiment, the logic for generating the alternative disk block allocation employs a random search approach, while in another embodiment, the logic for generating the alternative disk block allocation employs a heuristic approach.

Optimized application installation using disk block relocation

An apparatus is programmed with a plurality of programming instructions for generating, if possible, an alternative disk block allocation for a current disk block allocation that will yield reduced overall power consumption for a sequence of disk accesses. In some embodiments, the programming instructions include the logic for tracing the sequence of disk accesses to determine the current disk block allocation, the logic for generating the alternative disk block allocation, if possible, using the trace results, and the logic for effectuating the alternate disk block allocation, if generated. In one particular embodiment, the logic for generating the alternative disk block allocation employs a random search approach, while in another embodiment, the logic for generating the alternative disk block allocation employs a heuristic approach.

Method and apparatus for reducing power consumption by a disk drive

An intelligent bus bridge contained in a single integrated circuit chip along with computer systems and server systems that employ intelligent input/output subsystems. The intelligent bus bridge includes a local processor coupled for communication over a local component bus, a local memory controller that enables access to a local memory from the local component bus, and a component bus bridge that propagates accesses between the local component bus and a system component bus. The single integrated circuit chip enables dual-porting of the local memory controller without significant increases in input/output pins. A mode control input to the intelligent bus bridge indicates whether the intelligent bus bridge functions in a local master mode or a host master mode in a computer or server system.

Intelligent bus bridge for input/output subsystems in a computer system

An intelligent bus bridge contained in a single integrated circuit chip is disclosed along with computer systems and server systems that employ intelligent input/output subsystems. The intelligent bus bridge includes a local processor coupled for communication over a local component bus, a local memory controller that enables access to a local memory from the local component bus, and a component bus bridge that propagates accesses between the local component bus and a system component bus. The single integrated circuit chip enables dual-porting of the local memory controller without significant increases in input/output pins. A mode control input to the intelligent bus bridge indicates whether the intelligent bus bridge functions in a local master mode or a host master mode in a computer or server system.

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Portland, OR, United States of America

Rick Coulson