National Semiconductor Corporation

Rick C Jerome

Vida Ilderem

Alan G Solheim

Ali A Iranmanesh

Frank Marazita

Christopher S Blair

Madan Biswal

Rajeeva Lahri

Brian McFarlane

George E Ganschow

James L Bouknight

Ronald P Kovacs

Bamdad Bastani

Bancherd DeLong

Lawrence K Lam

Steve M Leibiger

Duncan A McFarland

Tad Davies

A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Method of fabricating BiCMOS device

A bipolar lateral device is disclosed having a high BV.sub.ceo. The device is formed according to a single polysilicon process. In one embodiment silicide is excluded from the surface of the N+ doped polysilicon protecting the N- base width region of the device and the resulting device has a BV.sub.ceo of 8 to 10 V. In another embodiment, the silicide is excluded from the surface of the polysilicon protecting the n-base width region and the polysilicon is maintained as intrinsic polysilicon. The resulting device has a BV.sub.ceo of about 20 V. The devices are useful as voltage clamping devices in programmable logic circuits which must withstand a collector to emitter reverse bias voltage that is sufficient to program either vertical fuse or lateral fuse devices.

Transistor device with increased breakdown voltage

A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emitter 44 extends about 0.2 microns from the upper surface and has a dopant concentration of about 8.times.1019 atoms of arsenic per cubic centimeter at the surface. A lightly doped base region 30 extends for about 0.46 microns below the emitter 44 to the collector 14. The upper surface of emitter 44 includes a metal contact 60. Heating the metal 60/emitter 44 interface to its eutectic melting point using a current or voltage pulse causes the aluminum to short through the emitter 44 to the base 30. Shorting the emitter programs the fuse. A second preferred embodiment uses polysilicon as an interconnecting medium. Mass transport of aluminum atoms through the polysilicon allows aluminum to collect at an interface between the polysilicon and an underlying single crystal silicon layer. Aluminum atoms are supplied from a contact metal. A barrier metal between the contact metal and an underlying polysilicon contact to the emitter is not present. Inhibiting or replacing a TiSi.sub.2 layer over the fuse emitter contact provides better reproducible fusing action. PtSi replaces TiSi.sub.2 if formed over the fuse emitter contact. Separate fuse base implants for the vertical fuse change BJT parameters for improved fusing characteristics. In still another preferred embodiment, codiffusing N type and P type dopants from the polysilicon emitter contact drops a separate fuse mask. The P type codiffused dopants diffuse ahead of the N type emitter dopants into the single crystal to change the base parameters to provide a decreased gain.

Vertical fuse device

Low resistance contacts for establishing an electrical pathway to an integrated surface substrate are provided. The pathway is formed by the connection of a p+ doped channel stop region with a p+ doped extrinsic layer. P+ doped polysilicon contacts are positioned on the substrate surface. In one embodiment, a metal silicide layer connects the polysilicon contacts and overlies the p+ doped extrinsic layer.

Low resistance silicided substrate contact

A BiCMOS method and device. The BiCMOS device achieves improved performance through the use of wraparound silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Method of fabrication of transistor device with increased breakdown

A method for formation of silicide structures on a semiconductor device. Oxide sidewalls are formed upon and selectively removed from polysilicon contacts. Refractory metal is deposited and heated, unreacted metal is removed, leaving a metal silicide on selected polysilicon sidewalls.

Formation of silicide contacts using a sidewall oxide process

A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

Reducing base resistance of a BJT by forming a self aligned silicide in

A BiCMOS device is revealed. The BiCMOS device achieves improved performance through the use of wrap-around silicide contacts, improved MOS gate formation, the use of n- and p-type LDD's, the formation of very shallow base regions in bipolar transistors, and through separate implants for base regions of the bipolar transistors and source/drains of the MOSFETS.

Interconnect method for semiconductor devices

An improved Schottky barrier diode for increasing the alpha particle resistance of static random access memories includes an extra implanted N-type region at the surface of the epitaxial layer to increase the impurity concentration there to about 1.times.10.sup.19 atoms per cubic centimeter. In one device, arsenic is employed to overcompensate a guard ring where the Schottky diode is to be formed, while in another device phosphorus is employed and the guard ring is not overcompensated. The resulting Schottky diodes, when employed in the static random access memory cells, dramatically increase the alpha particle resistance of such cells, while also substantially decreasing the access time.

Growing community of inventors

Puyallup, WA, United States of America

Rick C Jerome