International Business Machines Corporation

Mayo Foundation for Medical Education and Research

Rick Allen Philpott

Raymond Alan Richetta

Jonathan Darrel Coker

Timothy Joseph Schmerbeck

Robert Andrew Kertis

David Peter Swart

Donald Joseph Schulte

Chad Edward Mitchell

Christian J Goetschel

Richard Leo Galbraith

David R Holmes, Iii

Timothy A Schaefer

Gregory Scott Winn

Patrick Joseph Zabinski

Edward Brian Welch

Jaydip Bhaumik

Robert A Greene

Anthony Richard Bonaccio

Steven John Baumgartner

David W Siljenberg

Peter John Windler

David James Stanek

Mark Andrew Bergquist

A system provides for remote monitoring using asynchronous code division multiple access (CDMA) communication techniques between a base station and one or more transponders. Each transponder is attached or otherwise associated with an object or an environment to be monitored. Upon receipt of an interrogation signal, a transponder generates and transmits a coded transponder signal containing the monitored data. The coded transponder signal is generated using a spreading code. Each transponder is associated with a unique, mutually exclusive set of spreading codes. Each spreading code is based on a unique transponder address and the monitored data to be sent. A detector asynchronously monitors received signals for any of the available spreading codes. Once the detector detects a particular spreading code, the base station can identify the source transponder and extract the monitored data.

Asynchronous communication system for remote monitoring of objects or an environment

A termination block for connecting a first signal device and a second signal device. The termination block includes a housing, first and second pair of connectors, and an electrical circuit having passive elements that connect the first and second pair of connectors and provide impedance matching.

Differential signal termination block

Asynchronus communication system for remote monitoring of objects or an environment

A termination block provides a pair of coaxial connectors for a differential signal source and a pair of coaxial connectors for connection to a single ended coaxial input. Passive electrical components provide impedance matching while maintaining phase-matched true and complement signal paths for the differential signal.

A system and method provides for calibrating a corner frequency of a tunable filter coupled to a read channel of a data storage system to a desired frequency. A signal having a frequency equal to the target corner frequency is generated. A gain of the signal is adjusted to a gain threshold. The gain of the signal is then increased from the gain threshold by a pre-established amount, such as by 3 dB. The corner frequency of the signal is shifted until the gain of the signal is substantially equal to the gain threshold, at which point the corner frequency of the tunable filter is calibrated to the desired frequency. The signal generated is a peak-detectable signal. The corner frequency of a tunable filter may be a low or high corner frequency appropriate for filtering a data signal or a servo signal. The corner frequency calibration circuitry may be implemented in-situ the read channel circuitry of a data storage system.

System and method for calibrating a corner frequency of a tunable filter employed in a read channel of a data storage system

An apparatus and method for calibrating a cutoff frequency of a tunable filter, such as a tunable filter coupled to a read channel of a data storage system is disclosed. A calibration circuit includes a variable gain amplifier (VGA), an envelope detector, and a tunable filter coupled therebetween. A calibration signal having a preestablished frequency representing a specified cutoff frequency associated with the tunable filter is applied to the VGA. The gain of the amplifier is adjusted until an amplitude of an output signal provided by the filter is substantially equal to a first predetermined amplitude. A cutoff frequency of the filter is then adjusted until an amplitude of an output signal provided by the filter is substantially equal to a second predetermined amplitude, at which time the desired cutoff frequency of the tunable filter is precisely established. A single cutoff frequency or the low and high cutoff freqencies of a range of cutoff frequencies may be calibrated. The envelope detector includes a number of analog comparators which are used to compare an output signal provided by the filter with predetermined voltage amplitudes provided by first and second reference voltage sources. A control circuit controls amplifier gain and adjusts the cutoff frequency of the filter. A cutoff frequency calibration circuit according to the present invention may be advantageously implemented in-situ a read channel of a disk drive system.

System and method for adjusting a cutoff frequency of a tunable filter employed in a read channel of a data storage system

A system and method are provided for calibrating a corner frequency of a tunable filter using an ADC code difference method. A method for calibrating a corner frequency of a tunable filter in a direct access storage device includes generating a signal having a frequency within a pass band of the tunable filter to be passed to the tunable filter. The gain of the signal is adjusted to a first threshold level. The corner frequency of the signal is shifted to a second threshold level, whereby the corner frequency of the tunable filter is calibrated at a desired frequency. A system for calibrating a corner frequency of a tunable filter in a direct access storage device includes calibrate control logic coupled to a tunable filter. A signal source generating a signal having a frequency within a pass band of the tunable filter to be passed to the tunable filter is coupled to the tunable filter by a variable gain amplifier. An analog-to-digital converter (ADC) is coupled to the tunable filter. The ADC produces a digitized signal in response to receiving the signal from the filter. The calibrate control logic adjusts a gain of the digitized signal to a first threshold level. The calibrate control logic shifts the corner frequency of the digitized signal to a second threshold level, whereby the corner frequency of the tunable filter is calibrated at a desired frequency. The first threshold level is set to a first ADC code and the second threshold level is set to a second ADC code. The second threshold level, second ADC code is set to the equivalent code of any given attenuation setting, for example, about 3 dB less than the first threshold level, first ADC code.

System and method for calibrating a corner frequency of a tunable filter using ADC code difference method

An apparatus and method for estimating an amplitude of a readback signal obtained from a data storage medium and input to a gain modifying amplifier involves sensing an amplifier output signal in response to a readback signal applied to the amplifier. An amplifier control signal is produced which is representative of a difference between the amplifier output signal and a reference signal. A compensation signal associated with a temperature coefficient of amplifier gain is generated, and an estimate signal indicative of the amplitude of the readback signal is produced using the compensation signal. The estimate signal is representative of readback signal amplitude when the estimate signal has a magnitude equivalent to that of the difference signal and a polarity opposite that of the difference signal. Generating the compensation signal may further involve generating a first compensation signal having a magnitude proportional to absolute temperature and generating a second compensation signal having a magnitude independent of temperature. The first and second compensation signals may be selectively used to cancel temperature related gain and polarity variations in the amplifier control signal. A circuit for estimating an amplitude of a readback signal includes a variable gain amplifier, a temperature compensation circuit, and a comparator, all of which have an equivalent temperature profile and are provided on a common IC substrate. The circuit, which further includes an N-bit DAC and a logic circuit, may be implemented in a disk drive system.

Variable gain amplifier with temperature compensation for use in a disk drive system

A method for measuring an amplitude of a readback signal obtained from a data storage medium involves transmitting the readback signal to a gain modifying amplifier, such as a variable gain amplifier (VGA), preferably provided in the read channel. A voltage signal associated with a loop gain of the amplification circuitry is sensed and compared with a number of control voltage signals, each of the control voltage signals being associated with a corresponding digital word value. The digital word value associated with a control voltage signal that is equal to the sensed voltage signal represents the relative amplitude of the readback signal. Gain characterization circuitry may further be combined with readback signal amplitude measuring circuitry, preferably in-situ a read channel, to obtain the absolute amplitude of a readback signal. Gain characteristics of the amplification circuitry are determined by applying reference voltage signals associated with corresponding pre-established gain values to the signal input of the gain modifying amplifier. A control voltage signal is selectively applied to the amplifier for each of the reference voltage signals until the amplifier output voltage signal is substantially equal to a pre-established reference voltage signal. Amplitude measurements may thereafter be taken to obtain the absolute amplitude of readback signals. Readback signal amplitude measurements may be performed when the read channel is in a read mode, idle mode, or servo mode of operation.

Method for measuring relative and absolute amplitudes of a signal read from a data storage medium

A method and system for calibrating analog integrated circuits. Initially, a single calibration circuit is formed integral with a group of analog integrated circuits. A control signal and a calibration signal are generated from the calibration circuit. Next, the control signal and the calibration signal are selectively coupled to an input of a particular analog integrated circuit among the group of analog integrated circuits. The particular analog integrated circuit is then selected for calibration via the control signal. An output of the particular analog integrated circuit is thereafter observed, in response to enabling the particular analog integrated circuit for calibration via the control signal, such that if an output of the particular analog integrated circuit corresponds to the calibration signal, a successful calibration of the particular analog integrated circuit is indicated, thereby permitting the single calibration circuit to generically calibrate a multitude of diverse analog integrated circuits. The output of the particular analog integrated circuit is coupled to an input of the single calibration circuit, and the calibration value is incremented until the particular analog integrated circuit is calibrated, such that upon completion of the calibration, the calibration value comprises a current calibration value associated with the particular analog integrated circuit. In addition, if the output of the particular analog integrated circuit is composed of a logically high value, then an indication is provided that the particular analog integrated circuit has been successfully calibrated.

Method and system for adjusting and calibrating circuit parameters

An integrated delay line calibration method and apparatus are provided for a direct access storage device (DASD). A delay line, such as used in a direct access storage device (DASD) is calibrated by configuring the delay line as a ring oscillator for calibration. A delay line ring frequency is compared to a reference frequency. The delay of the delay line is adjusted until the delay line ring frequency and the reference frequency are equal. Each delay block within the delay line is controlled by a delay adjust digital-to-analog converter (DAC). A control logic circuit couples N-bit words to the delay adjust digital-to-analog converter (DAC) for calibration adjustment of the delay line delay.

Integrated delay line calibration method and apparatus for direct access

Methods and apparatus are provided for detecting servo information in a direct access storage device. A plurality of data symbols are read from a disk to produce a readback signal. Each data symbol and each sequence of data symbols contains servo identification information. A correlation filter provides a matched filter function of an expected readback signal of the plurality of data symbols to produce a correlated readback signal. A threshold detector is coupled to the correlation filter for identifying a threshold signal representative of the data symbol. A data separator responsive to the threshold detector windows the threshold signal and provides clock and data signals. The data separator includes a digital variable frequency oscillator (VFO) which optimally centers incoming servo information from the disk in a timing window and provides standard clocked data for a servo processor. The threshold detector has a variable threshold voltage that is programmed using a trim digital-to-analog converter (DAC).

Method and apparatus for servo data pattern detection

A charge pump that receives complimentary metal-oxide semiconductor (CMOS) input signals, has high noise immunity, low static error and works at low power supply voltages. The charge pump includes a current switch for receiving a control signal from a control circuit and for generating a charge signal, a loop filter having a first and second node, and a common-mode loop for sensing the charge signal from the current switch and for providing a voltage level adjustment signal to the first node of the loop filter in response thereto. The common-mode loop includes a sensing circuit for sensing the voltage level at the first and second node, an averaging circuit for producing an averaged voltage signal, a comparing circuit for comparing the averaged voltage signal to a reference signal to produce a feedback control output signal, and a feedback current source for adjusting the voltage level at the first node of the loop in response to the feedback control output signal.

Method and apparatus for providing a high speed charge pump with low

A method and apparatus are provided for translating small voltage continuous signals into large full supply signals to generate a clock signal. At least one oscillator input signal is applied to a first amplifier stage for generating an amplified voltage output signal. A first inverter is coupled to the first amplifier stage. A second inverter is coupled to the first inverter. An AC coupling capacitor couples the amplified voltage output signal to the first inverter input, and a feedback resistor is connected between the output and input of the first inverter.

Method and apparatus for generating a clock signal from a continuous

An integrated biquadratic, continuous-time filter section includes a plurality of operational transconductance amplifiers (OTAs). Simutaneously changing a transconductance (GM) of each of the OTAs is provided by adjusting a differential voltage applied to a plurality of differential transistor pairs of each OTA. Each of the OTAs include a plurality of current sources and a common mode feedback circuit for controlling a common mode output voltage level. Changing the transconductance of the OTA is independent of the common mode voltage level control.

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Rochester, MN, United States of America

Rick Allen Philpott