Isorg

Stmicroelectronics (grenoble 2) Sas

Richun Fei

Benjamin Bouthinon

Agathe Puszka

Quentin Chable

Salvador Mir

David Blanchon

Jocelyn Moreau

Pierre Muller

Noémie Ballot

A matrix-array detector having: an array of pixels arranged in a matrix along rows and down columns, each pixel for generating a signal according to a physical effect; a signal generator for generating two clock signals that are phase-shifted relative to one another; and a row-addressing device including a shift register, the shift register including a plurality of stages arranged in a cascade, each stage for receiving, in alternation from one stage to another, one clock signal from the two clock signals, and delivering an intermediate output signal that takes a high value and a low value allowing the pixels of the row to be activated and to be deactivated, respectively. The signal generator is also for generating a third clock signal. The addressing device further includes a plurality of isolation circuits, each isolation circuit connected between each stage and the corresponding row of the matrix, for receiving the third clock signal, the isolation circuit also for delivering a selection signal for selecting the corresponding row of the matrix when the intermediate output signal and the third clock signal are at the high level.

Matrix detector with reduced odd/even effect

A device includes a display screen and an image sensor. A first electromagnetic shielding layer permeable to light is arranged between active portions of the display screen and active portions of the image sensor.

Device integrating an image sensor and a display screen

Testing of control wires of a pixel array of an image sensor is performed by applying a signal transition to a control wire and detecting, based on a voltage signal detected on the control wire, the duration of at least part of the signal transition on the control wire. An electrical fault in the control wire is indicated based on a comparison of the detected duration to a threshold.

Circuit and method for on-chip testing of a pixel array

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Grenoble, France

Richun Fei