Intel Corporation

Richard Zhao

Chia-Pin Chiu

Russell S Aoki

Michael Zack Eckblad

Correy D Cooks

Chris Mozak

An embodiment of the present invention is a technique to assemble multi-core dice. A first socket has first N sets of front side bus (FSB) contacts to house a first package having first 2N dice. Each of the first 2N dice has M cores. N and M are positive integers. A first chipset has 2N FSB signal groups interfacing to the first package via the first N sets of FSB contacts using first N FSB signal groups of the 2N FSB signal groups.

Method and apparatus for assembling multi-core dice using sockets with multiple sets of front side bus contacts

An on-die termination method to support a multi-chip package routing topology is described. The on die termination method may increase the surface area on the substrate such that larger size die or more memory may be mounted thereto. The on-die termination method may include a semiconductor package that features on die termination bumps coupled to a semiconductor die's bus terminals, which couples the semiconductor die to an on-die termination pin coupled in the motherboard. An alternative on-die termination method includes a semiconductor die, within the multi-chip CPU package, designated as an end agent from which a single on die termination bump is coupled to an on-die termination pin.

On-die termination method for multi-chip packages

A method and assembly for utilizing a gasket to protect an exposed die from damage, such as chipping and cracking, caused by external forces such as shock, vibrations, installation and/or handling, as well as to prevent electromagnetic interference (EMI) emissions from the exposed die.

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Portland, OR, United States of America

Richard Zhao