Altera Corporation

Richard Yuan

Gregg William Baeckler

James G Schleicher

Mike Hutton

Bruce B Pedersen

Andy Louie Lee

David Lewis

Sinan Kaptanoglu

Henry Kim

Rahul Saini

Babette Van Antwerpen

Michael David Hutton

Yean-Yow Hwang

David Wolk Mendel

Vaughn Betz

Stephen D Brown

Terry Borer

Kevin Chan

Ian Chesal

Boris Ratchev

Yaska Sankar

Martin Langhammer

Joachim Pistorius

Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Omnibus logic element

Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Omnibus logic element for packing or fracturing

An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

Register retiming technique

Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Techniques for optimizing the placement and synthesis of a circuit design on a programmable integrated circuit are provided. The performance of a circuit design is analyzed after it has been compiled with different values for selected input parameters. The input parameter values that produce the best results for an output metric are then chosen to synthesis and place the circuit design on the programmable integrated circuit. In one embodiment, the values of the output metrics are averaged for all test compiles that share the same input parameters, but different seeds. In another embodiment, the compile with the best output metrics, as determined by the user, are selected. These techniques allow a user to automatically trade off compile-time to get a better-optimized circuit.

Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage

Logic circuits that support the addition of three binary numbers using hardwired adders are described. In one embodiment, this is accomplished by using a 3:2 compressor (i.e., a Carry Save Adder method), using hardwired adders to add the sums and carrys produced by the 3:2 compression, and sharing carrys data calculated in one logic element ('LE') with the following LE. In such an embodiment, with the exception of the first and last LEs in a logic array block ('LAB'), each LE in effect lends one look-up table (&#x201c;LUT&#x201d;) to the LE below (i.e., the following LE) and borrows one LUT from the LE above (i.e., the previous LE). The LUT being lent or borrowed is one that implements the carry function in the 3:2 compressor model. In another aspect, an embodiment of the present invention provides LEs that include selectors to select signals corresponding to the addition of three binary numbers mode.

Logic cell supporting addition of three binary words

A multiple-pass synthesis technique improves the performance of a design. In a specific embodiment, synthesis is performed in two or more passes. In a first pass, a first synthesis is performed, and in a second or subsequent pass, a second synthesis or resynthesis is performed. During the first synthesis, the logic will be mapped to for example, the logic structures (e.g., logic elements, LUTs, synthesis gates) of the target technology such as a programmable logic device. Alternatively a netlist may be provided from a third party. Before the second synthesis, a fast or abbreviated fit may be performed of the netlist to a specific device (e.g., specific programmable logic device product). Before the second synthesis, the netlist obtained from the first synthesis (or provided by a third party) is unmapped and then the second synthesis is performed. Since a partial fit is performed, the second synthesis has more visibility and optimize the logic better than by using a single synthesis pass. After the second synthesis pass, a more detailed fit is performed.

Physical resynthesis of a logic design

Techniques for mapping functions in a user design to lookup tables on a programmable integrated circuit are provided. Functions within a user design are rewritten as a composition of smaller, decomposed functions using a decomposition technique. An attempt is made to fit the decomposed functions into a lookup table configuration. If the decomposed functions do not fit into one the lookup table configurations for the programmable integrated circuit, the input variables are rotated within the user function. Then, an attempt is made to decompose the user function again based on the rotated input variables.

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Cupertino, CA, United States of America

Richard Yuan