Xilinx, Inc.

Richard Yachyang Sun

Raymond Kong

Daniel J Downs

John J Laurence

Sankaranarayanan Srinivasan

Sudip K Nag

Sandor S Kalman

John D Bunte

Sankaranarayanan Srinivasen

A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Method and arrangement providing for implementation granularity using implementation sets

A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.

Method and system for managing behavior of algorithms

A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing at least one set of high level rules into simple implementation directives. The method can further include the steps of selectively attaching the simple implementation directives to the data structure, implementing a task manager which queries a data structure node to create a list of tasks to be performed on the data structure, and executing the list of tasks using a generic flow engine.

Method and system for designing integrated circuits using implementation directives

A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.

Implementation set-based guide engine and method of implementing a circuit design

A method of implementing a user integrated circuit (IC) design in a tree representation includes the step of introducing the tree representation for the user IC design in a partitioned manner including at least one sub-design to form a design abstraction of the user design. At least one sub-design can include a sub-design providing for multiple levels of implementation hierarchy. The method can further include the step of traversing the design abstraction in a top-down fashion to provide functions selected among floor planning, port assignment, and timing budgeting for at least one sub-design, and the step of traversing the design abstraction in a bottom-up fashion to facilitate at least one among resolution of resource conflicts and parallel processing of multiple sub-designs. Traversing the design abstraction in the bottom-up fashion can facilitate a re-budgeting of timing for the integrated circuit design.

Method and system for implementing a circuit design in a tree representation

Routing algorithms can be modified to increase the number of programmable interconnect points (PIPs) used in a routing pattern. A file is set up to store information on whether a PIP has been covered. The cost of a node can be decreased by a predetermined value if two nodes are connected by an uncovered PIP. In another embodiment, a file is set up to store a count for each PIP. The count is increased each time the PIP is used in a routing. The cost of a node can be increased by multiplying a predetermined value and the count of a PIP associated with the node.

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Mountain View, CA, United States of America

Richard Yachyang Sun