Apple Inc.

Richard Y Su

Boon-Aik Ang

Dennis M Fischette, Jr

Meei-Ling Chiang

Samed Maltabas

Shaobo Liu

Yu Chen

Gregory N Santos

Pyoungwon Park

Litesh Sajnani

Hairong Yu

A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.

Reference clock switching in phase-locked loop circuits

Growing community of inventors

Santa Clara, CA, United States of America

Richard Y Su