Texas Instruments Corporation

Samsung Electronics Co., Ltd.

Richard X Gu

Daquan Huang

Hiep V Tran

A master voltage controlled oscillator (VCO) produces an output signal at an operating frequency of at least 100 gigaHertz (GHz). A buffer VCO injection-locked to an output of the master VCO produces an output signal at the operating frequency with a voltage swing greater than 50% of an output voltage swing of the master VCO output signal. The buffer VCO operates without pulling, and can drive a load of at least three times greater than a nominal load. Phase noise in the output of the buffer VCO is as much as &#x2212;96 decibels (dB) relative to the carrier (dBc) per Hertz (Hz) at 125 GHz with a 1 megaHertz (MHz) offset.

mmWave PLL architecture

One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise.

Systems and methods for cancelling phase-locked loop supply noise

There are numerous types of dividers that have been employed at various frequency ranges. For many very high frequency ranges (i.e., above 30 GHz), dividers in CMOS have been developed. However, many of these designs use multiple stages. Here, however, a single stage divider has been provided that is adapted to operate at very high frequencies (i.e., 120 GHz). To accomplish this, it uses parasitic capacitances in conjunction with inductor(s) to form an LC tanks so as to take advantages of parasitics that normal degrade performance.

Latch divider

Traditionally, low-noise amplifiers or LNAs have been used in high frequency applications, but for very high frequency ranges (i.e., 60 GHz), building an LNA to meet performance needs has been difficult. Here, however, an LNA has been provided that operates well around 60 GHz. In particularly, this LNA is generally unconditionally stable, has a generally low noise factor or NF, and has a generally high gain around 60 GHz.

Low-noise amplifier

The charge pump circuit includes: a charge pump output branch; a current leakage device coupled to the output branch; and a feedback device coupled between the output branch and a control node of the current leakage device such that the leakage device cancels leakage current from the output branch.

Charge pump output device with leakage cancellation

The charge pump circuit includes: a charge pump output branch having a first transistor and a second transistor coupled in series; an output branch replica having a third transistor and a fourth transistor coupled in series; a feedback circuit coupled between the output branch and the output branch replica; a charge pump input circuit coupled to the charge pump output branch, and having first and second input branches; and an input circuit branch replica controlled by the feedback circuit and coupled to the charge pump input circuit.

Rail-to-rail charge pump with replica circuitry

An oscillator circuit comprises a plurality of ring oscillators wherein each ring oscillator produces an oscillatory output signal. The ring oscillators are cross-coupled such that each ring oscillator drives only one other ring oscillator. In at least one embodiment, the oscillator circuit comprises four, three-stage ring oscillators. As such, each ring oscillator comprising three cells (e.g., inverters or delay elements). Further, in this embodiment, the oscillator circuit produces a four phase clock comprising the oscillatory output signals from each of the four ring oscillators.

Cross coupled voltage controlled oscillator

A time division multiplex data recovery system using a closed-loop phase lock loop (PLL) and delay locked loop (DLL) is disclosed. In other words, one closed loop comprises both a phase locked loop (PLL) and a delay locked loop (DLL) in a novel time division multiplex data recovery system. This new architecture comprises a 4 stage Voltage Controlled Oscillator (VCO) used to generate 8 clock signals, 45 degrees phase shifted from one another, for 8 receivers to do the oversampling. An interpolator tracks the received data signal and feeds it back to the Phase/Frequency Detector (PFD). The PFD has a second input of the reference clock which the PFD uses along with the interpolator input to correct the frequency of the PLL. The PLL operates at a high bandwidth. The DLL's bandwidth is several orders lower than the PLL. The DLL activates only a multiplexer and an interpolator continuously, thereby drawing a minimum amount of power.

Time division multiplex data recovery system using close loop phase and delay locked loop

In a transceiver unit including an adaptive equalizer filter unit, apparatus is provided for reducing or compressing the number of bits representing an error signal. The apparatus replaces a plurality of the most significant logic signal bits with a single bits while transferring the sign logic signal bit and the logic signal bits of lesser significance unchanged. Because of the reduction in the number of logic signal bits, the number of components implementing the multiplier unit in the adaptive filter unit can be reduced (i.e., in each stage of the adaptive filter). The reduction of the apparatus implementing the processing the error signal results in the same equilibrium value of the error signal, however, the time to reach this equilibrium value is increased.

Apparatus and method for an error signal compression technique in a fast adaptive equalizer circuit

A phase-locked loop circuit is disclosed. The phase-locked loop circuit includes a fundamental/quadrature phase comparator circuit (,) that compares an input bitstream (IN) to fundamental and quadrature phases of an output clock signal (CLK, CLKQ), to generate logic signals (I,, I,) corresponding to the state of the output clock signal phases at the time of each transition of the input bitstream. Compare logic (,) in the fundamental/quadrature phase comparator circuit (,) generates anticlockwise (A) and clockwise (C) signals to a state machine (,), in response to the logic signals (I,, I,) varying from a prior state (X,, X,) in opposing directions in a sequence; the sequence and directions are indicative of the polarity of the error frequency between the input bitstream and the output clock signal. Beginning with the first comparison and in response to the anticlockwise (A) and clockwise (C) signals, the state machine (,) issues a high gain charge or discharge signal (UPC, DNC) to a charge pump filter (,), to raise or lower the voltage (V,) at a capacitor (,) and thus increase or decrease the oscillation frequency of a voltage-controlled oscillator (,) that generates the output clock signal (CLK). This charge or discharge operation continues until the opposite one of the anticlockwise (A) and clockwise (C) signals is produced by the compare logic (,), at which time the state machine begins issuing lower gain discharge or charge signals (DND, UPD) to correct the output clock frequency in the opposite direction, in a fine correction manner.

Fast acquisition clock recovery using a directional frequency-phase detector

In a transceiver unit in which the information is encoded in a plurality of levels, a update unit for an adaptive or equalizer filter unit includes apparatus (,) for forming product of error signals and data signals without using a multiplier unit. The plurality of levels is represented by a logic signal format (b,, b,, b,) for five signal levels. The components of the logic signal format (b,, b,, b,) provide the control signals which process the error signals in such a manner as to provide the appropriate product. The only arithmetic unit is an adder unit (,) needed to combine the previous coefficient W,with the product generated by the apparatus (,).

Apparatus and method for equalizer filter units responsive to 5-level inputs signals

In a fast adaptive filter unit, an update unit replaces the multiplier unit which generates a product of the filter constant, the error signal and data signal and adding this product to a previously generated coefficient with a reduced complexity unit. The reduced complexity unit determines the sign of the product and whether the product is zero or non-zero. As a result of this determination a two bit signal is generated which is used to either increment or decrement the count in a register in the counter unit. The count held by the register is the coefficient signal, the coefficient signal being updated by each additional operation. In order to prevent the register from over-flowing, a second counter applies a signal periodically to the counter unit which decrements the magnitude of coefficient signal stored in the register by one count.

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Dallas, TX, United States of America

Richard X Gu