Ic Analytica, LLC

Qualcomm Incorporated

Tokyo Electron U.S. Holdings, Inc.

Richard Wunderlich

Joseph S Spector

Patrick G Drennan

Jon James Anderson

Mehdi Saeidi

Palkesh Jain

Chethan Swamynathan

Brian Degnan

An apparatus has a collection of ring oscillators. An instruction register block is configured to sequentially address and activate each ring oscillator in the collection of ring oscillators. A multiplexer with input lines is connected to each ring oscillator in the collection of ring oscillators and an output line. A pulse counter is connected to the output line of the multiplexer to count the number of oscillations of a selected ring oscillator within a selected time period to form a multiple bit frequency count output signal. A data shift register receives the multiple bit frequency count output signal and produces a serial frequency count output signal.

Apparatus and method for implementing a scalable digital infrastructure for measuring ring oscillators

An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Vertical and horizontal routing lines are in the scribe lines interconnecting the rows and columns of chips. Test circuit sites are in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.

Apparatus and method for testing all test circuits on a wafer from a single test site

An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.

Apparatus and method for managing power of test circuits

An integrated device that includes a substrate, a device level layer formed over the substrate, and interconnect portion over the device level layer. The device level layer includes a plurality of first device level cells, each first device level cell comprising a first configuration. The device level layer includes a plurality of second device level cells. At least one second device level cell includes a second configuration that is different than the first configuration. The plurality of second device level cells is located over at least one region of the integrated device comprising at least one hotspot.

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Austin, TX, United States of America

Richard Wunderlich