Xilinx, Inc.

Richard William Swanson

David P Schultz

Amitava Majumdar

Tao Pi

Ankur Jain

Anna W Wong

Steven P Young

Xiaobao Wang

Yohan Usthavia Frans

Trevor J Bauer

Brian C Gaide

Matthew H Klein

Wayne Edward Wennekamp

Terence J Magee

Qi Zhang

Anna Wing Wah Wong

Jongheon Jeong

Asim A Bajwa

Balakrishna Jayadev

Sanford L Helton

Arvind R Bomdica

Chiao K Hwang

Andy DeBaets

Siva Charan Nimmagadda

Jaeseo Lee

Srinivas Vura

Guoqing Ning

Suraj Ethirajan

Baanurathan Sadasivam

An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronous with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

Clocking architecture for communicating synchronous and asynchronous clock signals over a communication interface

An integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface communicates an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. A frequency of the interface clock signal is a multiple of a frequency of the logic clock signal.

Clocking architecture for communicating clock signals having different frequencies over a communication interface

In some examples, a system includes a clock source, a clock distribution network, and a plurality of clock generators. The clock source is configured to generate a global clocking signal. The clock distribution network is configured to fan out the global clocking signal to a plurality of loads. The plurality of clock generators is configured to receive the global clocking signal through the clock distribution network. Each clock generator of the plurality of clock generators is configured to generate a related clocking signal to the global clocking signal from the received global clocking signal. Each clock generator of the plurality of clock generators maybe configured to supply the global clocking signal or the related clocking signal to its respective load of the plurality of loads.

Global clock and a leaf clock divider

Methods and apparatus relate to a 1-to-2 memory interface deserializer circuit that, in a training mode, independently positions even and odd strobes in respective even and odd data windows. In an illustrative example, the deserializer circuit may receive a data signal that encodes even and odd data streams on the rising (even) and falling (odd) edges of a strobe clock signal. During a training mode, the deserializer circuit may independently determine, for example, an optimal temporal delay for each of the even strobe and the odd strobe. Adjustable delay lines dedicated to each of the even and odd strobe signals may simultaneously detect valid data window edges to permit determination of a desired delay to optimally position the strobe signals. Various embodiments may advantageously reduce jitter associated with asymmetric strobe and/or data signals to achieve a predetermined specification (e.g., timing margins) within the corresponding data windows.

Training and tracking of DDR memory interface strobe timing

In an example, a voltage-controlled oscillator (VCO) includes: an oscillator having a supply input; and a voltage regulator, coupled to the supply input. The voltage regulator includes: a first transistor and a second transistor providing a first source-coupled transistor pair, and a third transistor and a fourth transistor providing a second source-coupled transistor pair; an active load coupled to drains of the first, second, third, and fourth transistors; a first current source coupled to sources of the first and second transistors, and a second current source coupled to sources of the third and fourth transistors; a fifth transistor having a source and a drain coupled to the source and the drain, respectively, of the first transistor; and a sixth transistor having a source and a drain coupled to the source and the drain, respectively, of the third transistor.

Voltage-controlled oscillator with high and low gain options

An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

Recalibration of source synchronous systems

In an example, operating a PLL circuit includes generating an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency, generating a plurality of clock signals having an output frequency based on the error signal, and generating the feedback clock signal from the plurality of clock signals based on a first divider value and a control value derived from a second divider value. Operating the PLL circuit further includes multiplying each of a first integer value and a first fractional value by a power of two to generate a second integer value and a second fractional value, respectively, generating the second divider value using a sigma-delta modulator (SDM) based on the second integer value and the second fractional value, and dividing the second divider value by the power of two to generate the first divider value.

Fractional-N phase-locked loop with reduced jitter

In an apparatus relating generally to an IC die, the IC die has a regulated power supply, a power supply grid, and a test circuit. The regulated power supply is biased between a source supply node and a source ground node, which are externally accessible nodes of the IC die. An internal supply node of the power supply grid is coupled to the regulated power supply. The test circuit is coupled to the internal supply node of the power supply grid. The test circuit is configured to test for at least one short in the power supply grid. The test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance. The test circuit is configured to test for the at least one short in presence of background current leakage of the power supply grid.

Testing for shorts between internal nodes of a power distribution grid

An apparatus relating generally to time-to-digital conversion is disclosed. In this apparatus, a time-to-digital converter is coupled to a period sensor. The period sensor includes a pulse generator to generate a pulse. An integrator of the period sensor is coupled to receive the pulse to generate an analog voltage signal responsive to the pulse. The time-to-digital converter includes an analog-to-digital converter coupled to provide a digital signal associated with the analog voltage signal.

Time-to-digital conversion

A method of communicating with a source synchronous device can include determining an expected number of pulses of a strobe signal to be received in response to a first read request directed to the source synchronous device and receiving the strobe signal from the source synchronous device. Pulses in the strobe signal can be counted. Responsive to detecting a last pulse of the expected number of pulses of the strobe signal, the strobe signal can be replaced with a reference signal that is phase and frequency aligned with the strobe signal.

Strobe signal management to clock data into a system

An integrated circuit can include an input/output (I/O) bank. The I/O bank can include a plurality of byte clock groups. Each byte clock group can include at least one phaser configured to clock circuit elements of the byte clock group at a frequency at which a source synchronous device coupled to the byte clock group communicates data.

Input/output bank architecture for an integrated circuit

A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request.

Dynamic detection of a strobe signal within an integrated circuit

Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.

Clock distribution to facilitate gated clocks

A method of startup for a phase-locked loop (PLL) can include, at initiation of the PLL, providing a reference voltage from a startup voltage source to an input of a voltage controlled oscillator (VCO) in the PLL, wherein the reference voltage is set to a predetermined minimum voltage. The reference voltage can be stepwise increased from the predetermined minimum voltage. A frequency of a reference signal input to the PLL can be compared with a frequency of a feedback signal originating from an output of the VCO of the PLL to determine a frequency differential as the reference voltage increases. A determination can be made as to whether a convergence criterion is met according to the frequency differential. While the convergence criterion is not met, the reference voltage can be increased. When the convergence criterion is met, the reference voltage provided by the startup voltage source can be replaced with a voltage generated by an operational voltage source.

Phase-lock loop startup circuit and voltage controlled oscillator reference generator

A charge pump circuit has a charge pump section and a replica charge pump section. The replica charge pump section produces a replica voltage at which the UP current will match the DOWN current. A comparator compares the replica voltage to the output voltage, and adjusts the bias to the charge pump section and replica charge pump section so that the voltage level produced by the replica charge pump section matches the output voltage.

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San Jose, CA, United States of America

Richard William Swanson