Graphcore Limited

Microsoft Technology Licensing, LLC

Xmos Limited

Airbus Operations Gmbh

Richard William Osborne

Daniel John Pelham Wilkinson

Graham Bernard Cunningham

Stavros Volos

Cédric Alain Marie Fournet

Samuel Alexander Webster

Kapil Vaswani

Manuel Costa

Matthew David Fyles

Saurabh Mohan Kulkarni

David Thomas Chisnall

Martin Young

Douglas Watt

Stephen Felix

Simon Christian Knowles

Alan Graham Alexander

David Lacey

Balaji Vembu

Fabian Tschopp

Kenneth Gordon

Tim Hutt

Emmanuel Menage

Lars Paul Huse

Chad Jarvis

A peripheral device, for use with a host, comprises one or more compute elements a security module and at least one encryption unit. The security module is configured to form a trusted execution environment on the peripheral device for processing sensitive data using sensitive code. The sensitive data and sensitive code are provided by a trusted computing entity which is in communication with the host computing device. The at least one encryption unit is configured to encrypt and decrypt data transferred between the trusted execution environment and the trusted computing entity via the host computing device. The security module is configured to compute and send an attestation to the trusted computing entity to attest that the sensitive code is in the trusted execution environment.

Peripheral device

A processing system comprising one or more chips, each comprising a plurality of tiles is described. Each tile comprises a respective processing unit and memory, the memory storing a codelet. The processing system has at least one encryption unit configured to encrypt and decrypt data transferred between the tiles and a trusted computing entity via an external computing device. The codelets are configured to instruct the tiles to transfer the encrypted data by reading from and writing to a plurality of memory regions at the external memory such that a plurality of streams of encrypted data are formed, each stream using an individual one of the memory regions at the external computing device.

Streaming data to multi-tile processing system

A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

Synchronisation for a multi-tile processing unit

A computer comprising a plurality of processors, each of which are configured to perform operations on data during a compute phase for the computer and, following a pre-compiled synchronisation barrier, exchange data with at least one other of the processors during an exchange phase for the computer, wherein of the processors in the computer is indexed and the data exchange operations carried out by each processor in the exchange phase depend upon its index value.

Communication in a computer having multiple processors

A system and method for providing a set of data transfer instructions for converting one or more tensors between two different layouts. A first layout is used for storage of the data in host memory. A second layout is used for storage of the data in external memory accessible to a subsystem. The subsystem acts as a work accelerator to the host, and reads the external memory and processes the data read from the external memory. The first layout may be a logical representation of the tensor. The second layout is optimised for transfer to and processing by the subsystem. The data transfer instructions for converting between the two layouts are generated in dependence upon an analysis of the instructions to be executed by the subsystem.

Managed bulk memory

The invention provides a test apparatus for providing axial stresses in a structure, comprising a first set of formations for abutting a first surface of the structure at a first plurality of locations, a second set of formations for abutting a second surface of the structure at a second plurality of locations, and a force actuator, and wherein each set of formations comprises at least three formations and wherein at least two formations in each set of formations are aligned with a notional alignment line along the structure and at least one formation in each set of formations is out of alignment along the structure with said notional alignment line, such that when the force actuator applies a force, loads are applied at different locations, causing the structure to bend biaxially and thereby providing biaxial stresses in the structure.

Test apparatus for providing axial stresses in a structure

A method of generating a computer program, the method comprising: independently compiling a plurality of source code modules to generate a plurality of respective object modules comprising a plurality of respective threads explicitly designated by a user to be executed in parallel; in each of the object modules, inserting at least one symbol indicative of a property of the object module's thread potentially conflicting with a corresponding property of a thread of another of said object module as a result of parallel execution of those threads; executing a linker to perform a linking process on said object modules, the linking process comprising: assessing the symbols in conjunction with one another to determine whether a conflict exists between the threads of two or more of the respective object modules; and linking the object modules to generate a computer program in which said threads are executable in parallel, wherein the linking is performed in dependence on said assessment.

Compiling and linking

A method comprising: independently compiling a plurality of modules of source code to generate a plurality of respective object modules comprising a plurality of respective parallel threads explicitly designated by a user to be executed in parallel on a target platform; in each of the object modules, inserting at least one symbol indicative of a usage of a resource of the target platform associated with the respective thread; executing a linker to perform a linking process for linking the object modules, wherein the linking process comprises assessing the symbols in conjunction with one another, and based on the assessment generating an indication relating to a usage of the resource required for execution of the threads in parallel.

Link-time resource allocation for a multi-threaded processor architecture

Growing community of inventors

Bristol, United Kingdom

Richard William Osborne