Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Richard William Gregor

Pradip Kumar Roy

Isik C Kizilyalli

Samir Chaudhry

Sundar Srinivasan Chetlur

Sailesh Mansinh Merchant

Ranbir Singh

Edward Belden Harris

Chung Wai Leung

Michael Scott Carroll

Sylvia Thomas

Allen Yen

Sidhartha Sen

Daniel Joseph Vitkavage

Tony G Ivanov

Gerald W Gibson, Jr

Chun-Yung Sung

Jaseph R Radosevich

Michael Jay Parrish

Sidharta Sen

A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 &#x3bc;m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.

MOS transistor and method of manufacture

A semiconductor device having a capacitor integrated in a damascene structure. In one embodiment, the capacitor is formed entirely within a metallization layer of a damascene structure, having therein a semiconductor device component. Preferably, the capacitor is formed within a trench, having been etched in the dielectric material of the metal layer and the capacitor includes a first capacitor electrode formed within the recess in electrical contact with the device component of the metallization layer. An insulator may be formed over the first capacitor electrode, with a second capacitor electrode formed over the insulator. These elements are preferably conformally deposited within the trench, thereby forming a recess, a portion of which extends within the trench. A subsequently fabricated device component may then be placed in electrical contact with the second capacitor electrode.

Capacitor for a semiconductor device and method for fabrication therefor

A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 &mgr;m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.

Semiconductor device free of LLD regions

The present invention provides a semiconductor device, including an interconnect and a capacitor, and a method of fabrication therefor. The method includes forming a damascene interconnect structure through an interlevel dielectric layer and a dielectric etch stop layer located under the interlevel dielectric, wherein the damascene interconnect structure contacts a first interconnect structure. The method further includes forming a metal-oxide-metal (MOM) capacitor damascene structure through the interlevel dielectric layer and terminating on the dielectric etch stop layer. The damascene structures, may in an alternative embodiment, be dual damascene structures. Furthermore, the damascene interconnect structure and the MOM capacitor may, in another embodiment, make up part of a larger integrated circuit.

Damascene structure having a metal-oxide-metal capacitor associated therewith

The present invention provides a unique a resistor formed on a semiconductor substrate. The resistor preferably comprises a first resistor layer that includes a first metal silicide, such as tungsten silicide, and nitrogen and that is formed on the substrate. The first layer has a first thickness and a concentration of nitrogen incorporated therein. The nitrogen concentration may be varied to obtain a desired resistive value of the resistor. Thus, depending on the concentration of nitrogen, a wide range of resistive values may be achieved. The resistor further comprises a second resistor layer with a second thickness that includes a second metal silicide and that is formed on the first resistor layer. Thus, the present invention provides a metal silicide-based resistor having nitrogen incorporated therein which allows the resistance of the resistor to be tailored to specific electrical applications. Yet at the same time, the resistor is far less susceptible to temperature and voltage variation than conventional diffused resistors and, thereby, provides a more precise resistor.

Multi-layered metal silicide resistor for Si Ic's

A programmable semiconductor device and a method of manufacturing the same. The device includes: (1) a substrate composed at least in part of silicon, (2) a dielectric layer located over the substrate and (3) a control gate located over the dielectric layer wherein the dielectric layer contains a substantial concentration of an isotope of hydrogen.

Increased cycle specification for floating-gate and method of manufacture thereof

A semiconductor device and a method of manufacturing the semiconductor device. The device includes: (1) a substrate composed at least in part of silicon and (2) a film located over the substrate and having a substantial concentration of an isotope of hydrogen located in the film.

Deuterated direlectric and polysilicon film-based semiconductor devices

The specification describes intergate dielectrics between the floating silicon gate and the control silicon gate in MOS memory devices. The intergate dielectrics are composite structures of SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 with the first SiO.sub.2 layer grown on the floating gate,, and all layers preferably produced in situ in an LPCVD reactor. After formation of the composite SiO.sub.2 --Ta.sub.2 O.sub.5 --SiO.sub.2 dielectric, it is annealed at low pressure to densify the SiO.sub.2 layers. Electrical measurements show that the charge trap density in the intergate dielectric is substantially lower than in layered dielectrics produced by prior techniques.

Floating gate avalanche injection MOS transistors with high K dielectric

A method of suppressing damage to gate dielectrics by reducing the electrical field across the gate dielectric during plasma etching, photoresist stripping, or plasma assisted deposition of the overlying conductor to be etched. Openings in the gate oxide in the vicinity of the gates to be formed place the two conductive layers in contact with each other before the gates are formed and allows for the underlying conductive layer (usually the substrate) to be exposed to the plasma as the overlying unmasked conductive layer (usually polysilicon) is etched away. Preferably, the layer to be etched is deposited to be in contact with the underlying layer at the openings. This technique is applicable to integrated capacitor structures and other susceptible structures with a dielectric layer between two conductors.

Growing community of inventors

Winter Park, FL, United States of America

Richard William Gregor