Arm Limited

Arm IP Limited

Richard William Earnshaw

Kristof Evariste Georges Beyls

James Greenhalgh

Hugo John Martin Vincent

Alasdair Grant

Alejandro Rico Carro

Amyas Edward Wykes Phillips

Joshua Randall

Jose Alberto Joao

Geoffrey Wyman Blake

Spyros Lyberis

James Tsung-Lun Yang

Peter Guy Middleton

Scott Alan Douglass

An apparatus has processing circuitry (), and memory access circuitry () to control access to a memory system based on memory attribute data identifying each memory region as one of a plurality of region types. A speculation-restricted region type is supported, for which: at least when a first read request is non-speculatively issued to a region of the speculation-restricted type, a subsequent read request is permitted to be serviced using data obtained in response to the first read request; and for a speculatively issued read request to the region of the speculation-restricted type, at least when caching the read data would require allocation of a new entry in the cache, at least one response action, which is permitted for non-speculatively issued read requests specifying a target memory region of the speculation-restricted region type, may be prohibited from being performed before the first read request has been resolved as correct.

Speculation-restricted memory region type

An apparatus has processing circuitry to perform data processing in response to instructions; at least one control storage element to store internal state for controlling operation of the processing circuitry; and checksum generating circuitry to generate a checksum based on at least one item of internal state stored in the at least one control storage element. The checksum is stored in a diagnostic storage location from which information is accessible to a diagnostic control agent (e.g. software executing on the processing circuitry and/or an external device). This makes design of software test libraries for detecting hardware faults much more efficient.

Checksum generation

There is provided input circuitry to receive input data. Output circuitry outputs a sequence of instructions to be executed by data processing circuitry. Generation circuitry performs a generation process to generate the sequence of instructions using the input data with at least some of the instructions being grouped into functions. The sequence of instructions comprises an indirect control flow instruction comprising a field that indicates where a target of the indirect control flow instruction is stored. The target is an entry point to one of the functions and the generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation after execution of the indirect control flow instruction.

Speculation with indirect control flow instructions

An apparatus, method and computer program are described, the apparatus comprising decode circuitry configured to decode instructions, and processing circuitry responsive to the instructions decoded by the decode circuitry to perform data processing. In response to the decode circuitry decoding a memory copy size determining instruction specifying as operands a source memory address, a destination memory address and a total number of bytes to be copied from a source block of memory locations indicated by the source memory address to a destination block of memory locations indicated by the destination memory address, the processing circuitry is configured to determine, based on at least one of the source memory address and the destination memory address, a memory copy size indicating value indicative of a subset of the total number of bytes to be copied. A data transfer instruction is also described.

Memory copy size determining instruction and data transfer instruction

There is provided an apparatus including input circuitry that receives input data. Output circuitry outputs a sequence of instructions to be executed by data processing circuitry, at least some of the instructions being grouped into functions and generation circuitry performs a generation process to generate the sequence of instructions using the input data. The generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation performed during execution of the sequence of instructions and the stored state of control flow speculation is maintained between the functions.

Maintaining state of speculation between instruction functions

There is provided an apparatus that includes input circuitry to receive input data and output circuitry to output a sequence of instructions to be executed by data processing circuitry. Generation circuitry performs a generation process to generate the sequence of instructions using the input data. The sequence of instructions comprises an indirect control flow instruction having a field that indicates where a target of the indirect control flow instruction is stored. The generation process causes at least one of the instructions in the sequence of instructions to store a state of control flow speculation after execution of the indirect control flow instruction. The at least one of the instructions in the sequence of instructions that stores the state of control flow speculation is inhibited from being subject to data value speculation by the data processing circuitry.

Indirect control flow instructions and inhibiting data value speculation

According to the present techniques there is provided a data processing device, for applying to packaging, the device having a flexible substrate, the flexible substrate comprising: storage circuitry to store device data therein; processing circuitry to process the device data; and communication circuitry to communicate with a remote resource to transmit the device data thereto; sensor circuitry to generate sensed device data, and wherein the device is configured to store the sensed device data in the storage circuitry, process the sensed device data and/or transmit the sensed device data to a remote resource.

Device for applying to packaging

Aspects of the present disclosure relate to an apparatus comprising a requester master processing device having an associated private cache storage to store data for access by the requester master processing device. The requester master processing device is arranged to issue a request to modify data that is associated with a given memory address and stored in a private cache storage associated with a recipient master processing device. The private cache storage associated with the recipient master processing device is arranged to store data for access by the recipient master processing device. The apparatus further comprises the recipient master processing device having its private cache storage. One of the recipient master processing device and its associated private cache storage is arranged to perform the requested modification of the data while the data is stored in the cache storage associated with the recipient master processing device.

Growing community of inventors

Fulbourn, United Kingdom

Richard William Earnshaw