National Semiconductor Corporation

Richard Wendell Foote, Jr

Alexei Sadovnikov

Peter J Hopper

Vladislav Vashchenko

William David French

Terry Lee Lines

Punit Bhola

Robert Oliver

Peter B Johnson

Yaojian Leng

Andy Strachan

Erika Lynn Mazotti

Steven J Adler

Rodney L Hill

William Max Coppock

Victor Torres

Abhay Ramrao Deshmukh

Tom Bold

Joseph A De Santis

Joseph Anthony DeSantis

Edward F Pressley

Christoher J Knorr

A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.

Trench DMOS transistor with reduced gate-to-drain capacitance

A DMOS transistor with a lower on-state drain-to-source resistance and a higher breakdown voltage utilizes a slanted super junction drift structure that lies along the side wall of an opening with the drain region at the bottom of the opening and the source region near the top of the opening.

DMOS transistor with a slanted super junction drift structure

A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.

DMOS Transistor with a cavity that lies below the drift region

An improved method for manufacturing bipolar transistors is disclosed. The method for forming a PNP transistor comprises the steps of forming a P type collector on a substrate, forming a PNP epitaxial base on the P type collector, forming a PNP extrinsic base in the PNP epitaxial base, and forming a PNP emitter in contact with the PNP extrinsic base. The method for forming an NPN transistor comprises the steps of forming an N type collector on a substrate, forming a NPN epitaxial base on the N type collector, forming an NPN extrinsic base in the NPN epitaxial base, and forming an NPN emitter in contact with the NPN extrinsic base. The PNP and NPN transistors may be manufactured in the same control flow process.

Method for manufacturing bipolar transistors

A method for manufacturing a semiconductor apparatus is disclosed. The apparatus comprises double poly bipolar transistors and double poly metal oxide semiconductor (MOS) transistors. The bipolar transistors and the MOS transistors are manufactured in a unified process in which a first polysilicon layer (Poly) is doped to form the extrinsic bases in the bipolar transistors and to form the gates in the MOS transistors. A second polysilicon layer (Poly) is doped to form emitters in the bipolar transistors and to form the sources and drains in the MOS transistors. The method of the invention minimizes the number of manufacturing process steps.

Semiconductor apparatus comprising bipolar transistors and metal oxide semiconductor transistors and manufacturing method

A system and method is described for applying a pre-gate plasma etch in a semiconductor device manufacturing process in order to increase the integrity of a subsequently grown gate oxide layer. During the manufacture of a semiconductor device a sacrificial oxide layer is grown over a silicon substrate. The pre-gate plasma etch process is applied to the sacrificial oxide layer. Then the sacrificial oxide layer is stripped away and a gate oxide layer is grown over the silicon substrate. The gate oxide layer has an increased integrity due to the application of the pre-gate plasma etch process.

System and method for applying a pre-gate plasma etch in a semiconductor device manufacturing process

An efficient method is disclosed for increasing the breakdown voltage of an integrated circuit device that is isolated by a local oxidation of silicon (LOCOS) process. The method comprises forming a portion of a field oxide in an integrated circuit so that the field oxide has a gradual profile. The gradual profile of the field oxide reduces impact ionization in the field oxide by creating a reduced value of electric field for a given value of applied voltage. The reduction in impact ionization increases the breakdown voltage of the integrated circuit. The gradual profile is formed by using an increased thickness of pad oxide and a reduced thickness of silicon nitride during a field oxide oxidation process.

System and method for increasing breakdown voltage of LOCOS isolated devices

A method for manufacturing a semiconductor apparatus is disclosed. The apparatus comprises double poly bipolar transistors and double poly metal oxide semiconductor (MOS) transistors. The bipolar transistors and the MOS transistors are manufactured in a unified process in which a first polysilicon layer (Poly1) is doped to form the extrinsic bases in the bipolar transistors and to form the gates in the MOS transistors. A second polysilicon layer (Poly2) is doped to form emitters in the bipolar transistors and to form the sources and drains in the MOS transistors. The method of the invention minimizes the number of manufacturing process steps.

Semiconductor apparatus comprising bipolar transistors and metal oxide semiconductor transistors

A system and method is disclosed for providing improved trench isolation of semiconductor devices. An isolation trench of the present invention is manufactured as follows. A substrate of a semiconductor device is provided and a trench is etched in the substrate. Then a silicon liner is grown in the trench. The trench is then filled with polysilicon material. Polysilicon material is also deposited on top of the filled trench to protect the silicon dioxide liner from the effects of subsequent etch procedures and oxidation procedures. The initial height of the polysilicon material is selected to be large enough to allow the polysilicon material to survive the subsequent etch procedures and oxidation procedures.

System and method for providing improved trench isolation of semiconductor devices

A thin film resistor is formed to have very accurately defined dimensions which, in turn, allow the resistive value of the resistor to be very accurately defined. The resistor is formed on spaced-apart conductive pads which, in turn, are electrically connected to conductive plugs that are spaced apart from the resistor.

Thin film resistor and method of forming the resistor on spaced-apart conductive pads

A system and method is disclosed for using a differential wet etch stop technique to provide a uniform oxide layer over a metal layer in a laser trimmed fuse. A layer of boron doped oxide with a slow etch rate is placed over the metal layer. A layer of phosphorus doped oxide with a fast etch rate is placed over the boron doped oxide. The time period required for a wet etch process to etch through the phosphorus doped oxide is calculated. The wet etch process is then applied to the phosphorus doped oxide for the calculated time period. The wet etch process slows significantly when it reaches the boron doped oxide. This method forms a uniform layer of boron doped oxide over the metal layer.

System and method for providing a uniform oxide layer over a laser trimmed fuse with a differential wet etch stop technique

A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial silicon layer at the bottom of the central shallow trench. First and third doped layers are created in the epitaxial silicon layer adjacent to the central shallow trench. An oxide layer is then deposited to fill the three trenches. The second doped layer is diffused vertically down to the substrate. The first and third doped layers are diffused vertically down to the second doped layer. Lateral diffusion of the first and third doped layers is constrained by the oxide layer in the three trenches.

System and method for providing a deep connection to a substrate or buried layer of a semiconductor device

An oxidation process is used to produce a positional reference structure on a semiconductor wafer. A photolithographic mask layer used to define the positional reference structure can be combined with a photolithographic mask layer used to define an active device layer on the wafer, whereby both patterns can be printed in a single photolithographic operation. The same oxidation process used to produce an isolating oxide between active device regions of the active device layer can also be used to produce the positional reference structure.

System and method for using an oxidation process to create a stepper alignment structure on semiconductor wafers

Method for providing a deep connection to substrate or buried layer in a semiconductor device

A system and method is disclosed for providing a self heating adjustable titanium disilicon (TiSi) resistor. A triangularly shaped layer of polysilicon is placed a layer of insulation material. A layer of titanium is applied over the polysilicon and heated to form a layer of C49 type of TiSi. A current is then applied to the small end of the triangularly shaped layer of C49 TiSi. The current generates heat in a high resistance portion of the triangularly shaped layer of C49 TiSiand converts a portion of the C49 TiSito C54 TiSi. The lower resistance of the C54 TiSidecreases the effective resistance of the resistor. A desired value of resistance may be selected by adjusting the magnitude of the applied current.

Growing community of inventors

Kennedale, TX, United States of America

Richard Wendell Foote, Jr