Apple Inc.

Richard Warren Schreyer

Kenneth Christian Dyke

Michael James Elliott Swift

Alexander K Kan

Terence M Potter

Aaftab A Munshi

Gokhan Avkarogullari

Justin A Hensley

Michael Imbrogno

Jason P Jane

Luc R Semeria

Michael J E Swift

James J Ding

Scott James Forstall

Gregory B Novick

Patrick Y Law

Cahya Adiansyah Masputra

Gregory R Chapman

John Joseph Iarocci

Gordon J Freedman

Neil Gareth Crane

Damien Pascal Sorresso

Henry Graham Mason

Lucia Elena Ballard

Darren S Litzinger

Christopher Marcellino

Curtis Rothert

Michael Van Milligan

Charles Srisuwananukorn

Rahul U Joshi

David B Myszewski

Michael James Elliot Swift

Eric Albert

Joseph Sokol

Matthew G Waston

Thomas Brogan Duffy

Jeremy Sandmel

Ralph Clay Taylor

Robert D Kenney

Christopher A Burns

Ali Rabbani Rankouhi

Eric O Sunalp

Michael Jame Elliott Swift

Techniques are disclosed relating to ray intersection in the context of motion blur. In some embodiments, a graphics processor includes time-oblivious ray intersect circuitry configured to receive coordinates for a ray and traverse a bounding volume hierarchy (BVH) data structure based on the coordinates to determine whether the ray intersects with one or more bounding regions of a graphics space. In some embodiments, in response to reaching a temporal branch element of the BVH data structure, the ray intersect circuitry initiates a shader program that determines a sub-tree of the BVH data structure for further traversal by the ray intersection circuitry, where the sub-tree corresponds to a portion of a motion-blur interval in which the ray falls. This may provide accurate ray tracing for motion blur while reducing area and power consumption of intersect circuitry, relative to time-aware implementations.

Temporal split techniques for motion blur and ray intersection

Techniques are disclosed relating to specifying memory consistency constraints. In some embodiments, an instruction may specify, for a memory operation, a type of memory consistency and a scope at which to enforce the type of consistency. For example, these fields may specify whether to sequence memory accesses relative to the operation at one or more of multiple different cache levels based on the type of memory consistency and the scope.

Memory consistency in memory hierarchy with relaxed ordering

Systems, computer readable media, and methods for a unified programming interface and language are disclosed. In one embodiment, the unified programming interface and language assists program developers write multi-threaded programs that can perform both graphics and data-parallel compute processing on GPUs. The same GPU programming language model can be used to describe both graphics shaders and compute kernels, and the same data structures and resources may be used for both graphics and compute operations. Developers can use multithreading efficiently to create and submit command buffers in parallel.

System and method for unified application programming interface and model

Techniques are disclosed relating to synchronizing access to pixel resources. Examples of pixel resources include color attachments, a stencil buffer, and a depth buffer. In some embodiments, hardware registers are used to track status of assigned pixel resources and pixel wait and pixel release instruction are used to synchronize access to the pixel resources. In some embodiments, other accesses to the pixel resources may occur out of program order. Relative to tracking and ordering pass groups, this weak ordering and explicit synchronization may improve performance and reduce power consumption. Disclosed techniques may also facilitate coordination between fragment rendering threads and auxiliary mid-render compute tasks.

Resource synchronization for graphics processing

A compiler and library provide the ability to compile a programming language according to a defined language model into a programming language independent, machine independent intermediate representation, for conversion into an executable on a target programmable device. The language model allows writing programs that perform data-parallel graphics and non-graphics tasks.

Language, function library, and compiler for graphical and non-graphical computation on a graphical processor unit

Techniques are disclosed relating to a hardware-supported flexible data structure for graphics processing. In some embodiments, dimensions of the data structure are configurable in an X direction, a Y direction, a number of samples per pixel, and an amount of data per sample. In some embodiments, these attributes are configurable using hardware registers. In some embodiments, the data structure is persistent across a tile being processed such that local memory context is accessible to both rendering threads of a render pass and mid-render compute threads.

Local image blocks for graphics processing

Techniques are disclosed relating to performing mid-render auxiliary compute tasks for graphics processing. In some embodiments, auxiliary compute tasks are performed during a render pass, using at least a portion of a memory context of the render pass, without accessing a shared memory during the render pass. Relative to flushing render data to shared memory to perform compute tasks, this may reduce memory accesses and/or cache thrashing, which may in turn increase performance and/or reduce power consumption.

Mid-render compute for graphics processing

In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator that may control whether or not the GPU captures and/or responds to communications from another processor (e.g. a central processing unit (CPU) that executes a driver associate with the GPU). A snooze indicator may control whether or not the GPU is automatically repowered at the start of the next frame, or is repowered only if the communication indicating additional work has been received. In an embodiment, the GPU mode controls discussed above may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.

Graphics hardware mode controls

An image may be divided into tiles, each tile including a multitude of pixels. For each tile, a list of primitive groups that intersect the tile and an initial list of volumes that intersect the tile may be generated. For each primitive group in the list of primitive groups, a per-primitive group list of volumes may be generated. The per-primitive-group list of volumes may include volumes from the initial list of volumes whose depth range overlaps with a depth range of the primitive group. Pixels in the tile which intersect the primitive group may be shaded using the per-primitive-group list of volumes.

Tiled forward shading with improved depth filtering

A plurality of asynchronous command streams are established. A first command stream shares a common resource with a second command stream. A synchronization object is incorporated into the first command stream. A central server arbitrates serialization of the first and second command streams using the synchronization object. The central server arbitrates serialization without direct communication between the first and second command streams.

Serialization of asynchronous command streams

In an embodiment, a processor that includes multiple cores may implement a power/performance-efficient stop mechanism for power gating. One or more first cores of the multiple cores may have a higher latency stop than one or more second cores of the multiple cores. The power control mechanism may permit continued dispatching of work to the second cores until the first cores have stopped. The power control mechanism may prevent dispatch of additional work once the first cores have stopped, and may power gate the processing in response to the stopping of the second cores. Stopping a core may include one or more of: requesting a context switch from the core or preventing additional work from being dispatched to the core and permitting current work to complete normally. In an embodiment, the processor may be a graphics processing unit (GPU).

Graphics power control with efficient power usage during stop

Growing community of inventors

Scotts Valley, CA, United States of America

Richard Warren Schreyer