Standard Microsystems Corporation

Smsc Holdings Sarl

Richard Wahler

Alan David Berenbaum

Eileen Marando

Raphael Weiss

John D Virzi

Robert W Schoepflin

Ronald W Streiber

Drew Jon Dutton

Kevin Harney

Steven Burstein

Jay D Popper

Randy B Goldberg

Wayne A Miller, Jr

Robert Gross

Donald D Noviello

Richard H Boz

Carl Schooley

A system to control access to a nonvolatile memory. The system includes an embedded controller, and a nonvolatile memory including a password. The embedded controller and the nonvolatile memory may be in communication with one another. The system further includes a lock register receiving and storing the password from the nonvolatile memory, and a key register receiving a key from the embedded controller and holding the key for one machine cycle. Further, the system includes a comparator connected between the lock register and the key register. The comparator compares the password received from the lock register and the key received from the key register. Output from the comparator is provided to an access filter connected between the embedded controller and the nonvolatile memory. Based on the comparator output, the access filter may grant or block access to the nonvolatile memory.

Method and system for controlling access to embedded nonvolatile memories

The present disclosure provides an improved point-to-point serial peripheral interface, a system comprising an improved point-to-point serial peripheral interface, and a method for use in a system comprising an improved point-to-point serial peripheral interface. A master comprises a SPI initiating port. Each slave comprises at least one SPI receiving port and at least one SPI forwarding port. The master provides a set of SPI signals to the SPI receiving port of the first slave in the chain, and the entire SPI signals are forwarded via the SPI forwarding port of each of the slaves until the SPI transaction reaches a target slave, which is identified by an in-band device addressing mechanism.

Point-to-point serial peripheral interface for data communication between devices configured in a daisy-chain

System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller.

Implementation of one time programmable memory with embedded flash memory in a system-on-chip

Temperature readings obtained within a computer system from the location of monitored circuit elements may be oversampled at least three times, and a median average of the three parameter readings rather than the arithmetic mean may be used for controlling a device, e.g. a fan, configured to regulate the environmental parameter, e.g. temperature, a the location of the monitored circuit elements. For example, when a CPU temperature reading is requested by the system comprising the CPU, a thermal monitoring system may acquire at least three consecutive temperature readings of the CPU, discard the highest temperature reading and the lowest temperature reading, and return the median reading to be used in controlling a fan configured to regulate temperature at the location of the CPU, resulting in more accurate temperature readings and more accurate fan control. In various implementations, more than three readings may be considered at a time, and running averages based on median values may be computed in a variety of ways to obtain a temperature control value to control the fan.

Processor temperature measurement through median sampling

System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g., TPM, to query the system for system state information, and verify that the system has not been compromised.

Enhancing security of a system via access by an embedded controller to a secure storage device

A method and apparatus for operating a portable computer configured for docking to a docking station is disclosed. In one embodiment, a portable computer system includes a docking interface having a bus switch and a bus monitoring circuit, and a bus coupled to the docking interface. With the computer coupled to a docking station, the bus switch, when closed, may couple the bus to a peripheral interface in the docking station. The bus switch may close responsive to docking, thereby completing the electrical coupling of the bus to the peripheral interface in the docking station. The portable computer being docked to the docking station, the bus monitoring circuit may monitor the bus cycles occurring on the bus and identify trusted read and/or write cycles. During trusted bus cycles the monitoring circuit may operate to open the bus switch thereby preventing information transmitted during the trusted cycles to be accessible outside of the portable computer system, even with the portable computer system remaining docked to the docking station. The monitoring circuit may also operate to close the bus switch in response to a currently occurring trusted bus cycle being interrupted, aborted and/or completed.

Trusted LPC docking interface for docking notebook computers to a docking station

A resistor/capacitor identification detection (RCID) circuit may provide system level identification of hardware (e.g. circuit board ID) through a single pin interface, by identifying up to a specified number of more than two quantized RC time constant states by measuring the discharge and charge times of an external RC circuit coupled to the single pin. The RCID circuit may initiate the discharge followed by a charging of the external RC circuit. The signal developed at the signal pin may be provided to the input of a threshold detector, with the threshold set at a specified percentage of a supply voltage used for operating the RCID circuit. The digitized output of the threshold detector may be used to gate a counter, after having been filtered through an input glitch rejection filter. A resolution of the counter may be determined by a high frequency clock used for clocking the counter. The numeric values of the charge and discharge times may be stored in data registers comprised in the RCID circuit.

Resistor/capacitor based identification detection

A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the first number may also include increasing the number of first binary values in the binary field. Additionally, a second number indicating a second portion of the current number of the counter may be stored in another portion of memory. The second number may specify the number of times the first binary values has comprised the entirety of the binary field. Thus, the first number and second number may specify the current number of the counter. Storing the first and second number may be performed a plurality of times to implement a counting function of the counter.

Method for implementing a counter in a memory with increased memory efficiency

In one embodiment, a monitoring device (e.g., a slave device) may be configured to perform a plurality of monitoring functions. For example, the monitoring device may comprise a watchdog timer configured to monitor communications between the processing unit (e.g., a host processor) and the monitoring device. The watchdog timer may cause the monitoring device to enter a failsafe mode of operation if the processing unit fails to communicate with the monitoring device within a predetermined period of time. Additionally, the monitoring device may be configured to perform thermal management functions via one or more temperature sensors. The monitoring device may enter the failsafe mode of operation if a sensed temperature exceeds a predetermined temperature limit. Furthermore, the monitoring device may also comprise a status unit that is operable to provide the processing unit an indication of a state of the monitoring device.

Failsafe slave mechanism for mission critical applications

An apparatus and method for handling an interrupt are disclosed. In one embodiment, a processor may receive an interrupt request corresponding to a particular interrupt. The particular interrupt may be one of a group of interrupts. Responsive to receiving the interrupt request, the processor may substitute a vector corresponding to the group of interrupts with a vector corresponding to the particular interrupt. Responsive to the substitution, the processor may then jump to a service routine corresponding to the particular interrupt. Execution of the service routine may resolve the condition which initially caused the interrupt request.

Method and apparatus for handling interrupts

A double buffered flash bank. In one embodiment, a flash interface may be programmed by a register interface with a first set of data while a second set of data is being written to the register interface. In one embodiment, flash banks may be programmed in parallel using latched register interfaces. For example, while data from a first register interface is being written to the first flash bank and data from a second register interface is being written to a second flash bank, new data may be written to the first register interface and to the second register interface. The new data may then be written from the first register interface to the first flash bank and from the second register interface to the second flash bank.

Double buffered flash programming

A system may include a tachometer reading unit and a PWM (Pulse Width Modulated) signal generator configured to generate a PWM signal. The tachometer reading unit may be configured to obtain a tachometer reading from a tachometer signal generated by a device powered by the PWM signal. The tachometer reading unit includes a register configured to store a value indicative of a maximum stretching duration. The tachometer reading unit is configured to update the register in response to receiving a new value of the maximum stretching duration. The tachometer reading unit may be configured to control the PWM signal generator to stretch a pulse in the PWM signal and to not stretch the pulse longer than the maximum stretching duration indicated by the register. The tachometer reading unit is configured to obtain the tachometer reading during the stretched pulse in the PWM signal.

Programmable PWM stretching for tachometer measurement

A system and method for increasing resolution of pulse width modulated (PWM) signal duty cycle calculations in a fan speed control system operating to control rotational speed of at least one fan. The method may comprise obtaining a temperature reading from a first temperature sensor in the fan speed control system during a first time period. The temperature reading has resolution of a first number of bits. A portion of the first number of bits is selected for calculating a PWM signal duty cycle with the resolution of the first number of bits in the temperature reading using only the portion of the first number of bits and zone parameters associated with the first temperature sensor. The PWM signal duty cycle may then be converted into a PWM signal that may be provided to the at least one fan.

Fan control system with improved temperature resolution

A method and apparatus for hot-docking is disclosed. In one embodiment, a portable computer system includes a bus bridge and a bus coupled to the bus bridge. The bus may have one or more peripheral devices or peripheral interfaces coupled to it. The bus may also be coupled to a docking interface having a bus switch. The bus switch, when closed and the computer is coupled to a docking station, may couple the bus to a peripheral interface in a docking station. The bus switch may close responsive to docking, thereby completing the electrical coupling of the bus to the peripheral interface in the docking station. The closing of the bus switch may be controlled by the docking interface such that operations on the bus are not interrupted during the docking procedure.

Switchable hot-docking interface for a portable computer for hot-docking the portable computer to a docking station

A data separator for use in synchronizing data derived from a floppy disk or similar data source provides a variable net gain or loss of charge to vary the frequency of a voltage-controlled oscillator in accordance with the relative position of the data with respect to the clock until data centering or synchronization is achieved. The net charge is derived from a charge pump circuit that is controlled by a charge pump-up signal whose duration is proportional to the detected phase difference between the data and the clock, and a charge pump-down signal whose duration is one clock cycle. When the data pulse is centered within a clock cycle, the duration of a pump-up signal is one half that of a pump-down signal.

Growing community of inventors

St. James, NY, United States of America

Richard Wahler