International Business Machines Corporation

Richard W Voorhees

Don S Keener

Andrew B McNeill

Thomas H Newsom

Gregory J Moore

Edward I Wachtel

Kevin L Scheiern

Gregory F Bush

Jeanne E Morel

This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer system has a high speed local processor data bus, at least one logical processor device coupled directly to the local processor bus and capable of signalling through the local processor bus an occurrence of the transfer of blocks of data, and a storage controller coupled directly to the local processor bus for regulating communications between the processor device and storage memory devices. The storage controller has a FIFO memory for transitory storage of blocks of data being exchanged with the local processor bus and is capable of signalling through the local processor bus the state of the FIFO memory. The processor device and storage controller cooperate for exchange of blocks of data between the local processor bus and FIFO memory when the FIFO memory has available one of data to be transferred and space for reception of data and for emptying of the FIFO memory through the local processor bus as necessary.

Personal computer system having high speed local processor bus and

Arrangements for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

Physical partitioning of logically continuous bus

This invention relates to personal computers and, more particularly, to a personal computer having an interface controller providing an economical way to achieve access to a direct access storage device by a small computer system interface. In accordance with this invention, the system CPU is selectively allowed to access all or only a portion of the internal registers in an interface controller, enabling implementation in conjunction with a conventional subsystem microprocessor interface to the registers if desired. With this change, either interface has full access to the interface controller's internal registers. By allowing such access, the number of component parts required can be reduced where multitasking possibilities are not desired, and the cost of providing SCSI capability significantly reduced.

Personal computer with interface controller

In order to more effectively use read only memory space of a personal computer system, ROM code is selectively located or mapped to either an address boundary which is an even or odd integer multiple of one half the capacity of the read only memory device in which the ROM code is stored. The ROM code is stored in the read only memory device in two fields. In a first field, the ROM code is broken up into two segments, and the first segment precedes the second segment. In the second field, the same two segments are stored, but the second segment is stored preceding the first segment. A register, for storing page select bits, provides an input to an address decoder and an input to an adder, which adds unity to the contents of the register and provides its outputs to the address decoder as well. Accordingly, the address decoder will respond to either the page which is identified by the page select bits or the page following the identified page. The LSB of the page select bits is used in addressing the read only memory device to select between the first field (selected when the LSB is zero) or the second field (selected when the LSB is unity).

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Boca Raton, FL, United States of America

Richard W Voorhees