Vlsi Technology, Inc.

Acoustic Technologies, Inc.

Richard W Ulmer

Elie Georges Khoury

James Ward

Samuel L Thomasson

Joseph Alan Thomsen

Laura Elisabeth Simmons

Kendall G Moore

Sung-Hun Oh

Comparators, memory devices, comparison methods and memory reading methods are provided. One aspect provides a comparator including an input stage having a data input adapted to receive a data voltage signal, a reference input adapted to receive a reference voltage signal, and a plurality of current sources individually coupled with one of the data input and the reference input and individually configured to convert one of the data voltage signal and the reference voltage signal to a differential current signal and to output the differential current signal; and a comparator stage including a plurality of inputs configured to receive the differential current signals from the input stage and the comparator stage being configured to compare the differential current signals and to output an output signal indicative of a comparison of the differential current signals.

Memory devices and memory reading methods

Sound is converted into an electrical signal by a microphone and is converted into an inaudible, digitally modulated signal that is combined with the electrical signal from the microphone, amplified, and converted into sound waves by a speaker. Any sound traveling from the speaker back to the microphone includes the inaudible component representing the original sound. The inaudible component is separated from the audible components, and the original sound is reconstructed in a digital demodulator. The reconstructed original sound is subtracted from the signal from the microphone, thereby reducing any echo and canceling feedback. Digital modulation includes any form of shift keying, including coherent and noncoherent techniques for modulating frequency, phase, or amplitude.

Reducing acoustic feedback with digital modulation

Comparators and comparison methods

The present invention relates to a process control monitoring system and method. The system and method uses current comparator circuits for monitoring process changes. Process sensitive current sources are compared with weighted reference current sources in a manner that each output of the current comparators demonstrates the inequality of the current sources. By setting the weighted reference current sources properly, the outputs of the current comparators may be used to locate the process corner of the fabricated integrated circuit.

Process control monitoring system and method therefor

A low-skew CMOS clock divider circuit for providing tracking of the divide-by-one and divide-by-two output signals obtained from a source of master clock pulses is fabricated using two matched flip-flops externally wired as divide-by-two devices. Coincidence gates are coupled with the outputs of the flip-flops to produce the desired divide-by-one and divide-by-two output signals in a manner such that the signals in each path pass through substantially identical circuit components, Thus, any delays encountered are the same in both circuit paths. In this manner, skew between the edges of the divide-by-two and divide-by-one clock signals is significantly reduced.

Low skew CMOS clock divider

A logic level shifter characterized by a first inverting stage which shifts an input signal downwardly to a lower level, and a second inverting stage which shifts the lower level upwardly to an output signal level which is greater than the input signal level. Feedback from the output is used to virtually eliminate static current drain when the input logic level is 0. The method of the invention involves downwardly shifting an input range of voltages to a lower range of voltages, and then upwardly shifting the lower range of voltages to an output range of voltages which is greater than the input range of voltages. There is preferably a first inversion in the downward shift and a second inversion in the upward shift. A sensing step senses the output voltage to reduce the static current consumed by the process.

Logic level shifter for 3 volt CMOS to 5 volt CMOS or TTL

A self-configuring clock interface circuit automatically configures itself according to the type of clock input signals applied to two input terminals interconnected with the interface circuit. The system includes a pair of counters connected to the input terminals and having their outputs connected to the two inputs of an Exclusive NOR gate which acts as a control device for the system. The output of the exclusive NOR gate is coupled to a 2:1 multiplex to control the interconnection of one or the other of two inputs to the multiplex circuit with a clock output for the interface circuit.

Self-configuring clock interface circuit

A CMOS crystal oscillator circuit for producing a 32 KHz clock signal operates at low power over a range of power supply voltages without overdriving the crystal. To accomplish this, the complementary MOS transistors in the oscillator inverter are supplied with operating current from a constant low current source. The constant low current is at an optimum value for crystal stability and power consumption and is independent of supply voltage variations. To ensure quick initial start-up of the oscillator circuit, a second current source is connected in parallel with the constant current source; and the second source initially is switched on for a pre-established time interval to supply significantly greater operating current to the oscillator inverter only during initial start-up of the oscillator. After this pre-established time interval, the second current source is rendered inoperative or non-conductive for the duration of the operation of the oscillator circuit.

Growing community of inventors

Tempe, AZ, United States of America

Richard W Ulmer