Motorola Corporation

Richard W Ulmer

Stephen H Kelley

Roger A Whatley

Robert N Allgood

Robert D Lee

Henry Wurzburg

Robert R Beutler

James A McKenzie

James A Miller

A voltage detecting circuit is provided for generating an output signal when an input signal exceeds the power supply voltage by a predetermined amount. A reference current is established by an output stage using a first current mirror. A second current mirror is connected to the output stage and detects the input voltage level by forcing a greater or lesser amount of current through the output stage to provide a high or low level output voltage.

High voltage detection circuit

An MOS current limit circuit which provides current limiting protection is provided. A driver transistor of a conventional output stage is coupled to a current limiting transistor which is one transistor of a current mirror. The current limiting transistor of the current mirror has the V.sub.GS thereof accurately biased to insure a precise current limit value. When the current limiting transistor is not performing a current limiting function, the current limiting transistor is made conductive and further provides high voltage protection to the driver transistor when the driver transistor is nonconductive.

MOS current limiting output circuit

A buffer circuit comprising a current source transistor, a switching transistor and a current sink transistor coupled in series is provided. Control electrodes of the switching transistor and current sink transistor are directly connected and coupled to an input voltage. The buffer circuit has an accurate switchpoint voltage which is substantially process and temperature independent, and the circuit does not consume power for input voltages having low and high CMOS levels.

TTL to CMOS input buffer circuit for minimizing power consumption

An analog switch structure which utilizes three switches and has low leakage current is provided. A first switch couples an input terminal to a node in response to a control signal. A second switch connects the node to an output terminal in response to the control signal. A buffer circuit is connected to the output terminal for providing a buffered output signal. A third switch is connected between the buffered output signal and the node to selectively connect the buffered output signal to the node, thereby maintaining zero voltage potential across the second switch.

Analog switch structure having low leakage current

An on-chip voltage generator circuit is disclosed having an output voltage which is reduced by a predetermined amount from a supply voltage. The output voltage is proportional to the gate-to-source voltages of two complementary transistors and varies with temperature and processing in a similar manner with digital circuitry on the chip for which the output voltage may be used to operate. A current source is used to provide a known current to the two complementary transistors and a buffer is used to provide a low impedance output.

Voltage generator circuit having compensation for process and

A voltage compatible circuit for providing TTL and CMOS level inputs and/or outputs is provided. An input signal level detection portion generates either a CMOS or a TTL mode signal in response to a voltage level selection signal. One or more input buffers and/or output buffers is coupled to the CMOS and TTL mode signals. The input buffers are responsive to input signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. The output buffers provide output signals within predetermined CMOS voltage levels in response to a voltage level signal having at least a predetermined value determined by the input signal level detection portion and within predetermined TTL voltage levels otherwise. A reference voltage portion and a bias generator portion are coupled to the input and output buffers to provide the predetermined voltage levels.

Circuit for interfacing with both TTL and CMOS voltage levels

A power-on reset circuit which deletes the need for resistors uses a current source transistor and a capacitor to provide a minimum time for the power-on reset signal. A load transistor replaces a resistor in a portion of the circuit which provides a reference.

MOS Power-on reset circuit

An operational amplifier capable of selectively performing a variety of circuit functions is provided. A single operational amplifier utilizes switched capacitors for sampling and holding an input signal, for establishing a low frequency pole, for applying the sample to an output capacitance to charge the capacitance and for comparing the input signal with a reference. The multi-function circuit provides a large savings in circuit area and permits versatility of circuit applications. One embodiment of the invention is to utilize a companding DAC having a capacitor array which may be used as the output capacitance of the operational amplifier circuit. The DAC provided utilizes an R ladder DAC coupled directly to a C DAC and has a switching structure that is simpler than comparable prior art circuits. The DAC is asynchronous and has programmable A- and Mu-255 law PCM conversion capability. Coupled directly to the C DAC is an operational amplifier receive filter circuit which utilizes the C DAC as an input capacitor thereby eliminating the need for a buffer amplifier and allowing the DAC to be used for both analog to digital and digital to analog conversion.

Capacitive DAC to filter interface circuit

A CMOS operational amplifier includes a biasing scheme for supplying current to a differential stage. A push-pull output stage includes a current sinking transistor which is coupled to a first output of the differential stage. A current mirror is coupled between a second output of the differential stage and the gate electrode of a current sourcing device in the output stage.

CMOS Operational amplifier employing push-pull output stage

A temperature stable bandgap voltage reference source utilizing two substrate bipolar transistors biased at different emitter current densities is provided. Switched capacitors are used to input the V.sub.be and the .DELTA.V.sub.be of the transistors (NTC and PTC voltages, respectively) into an amplifier to provide a reference voltage proportional to the weighted sum of the PTC and NTC voltages. Proper selection of the ratio of the switched capacitors renders the reference voltage substantially independent of temperature. In a modified form of the reference, the reference amplifier is implemented by an auto-zeroed operational amplifier which uses switched capacitor techniques and an integrated capacitor to achieve the auto-zeroing function.

Switched capacitor temperature independent bandgap reference

An operational amplifier capable of selectively performing a variety of circuit functions is provided. A single operational amplifier utilizes switched capacitors for sampling and holding an input signal, for establishing a low frequency pole, for applying the sample to an output capacitance to charge the capacitance and for comparing the input signal with a reference. The multi-function circuit provides a large savings in circuit area and permits versatility of circuit applications. One embodiment of the invention is to utilize a companding DAC having a capacitor array which may be used as the output capacitance of the operational amplifier circuit. The DAC provided utilizes an R ladder DAC coupled directly to a C DAC and has a switching structure that is simpler than comparable prior art circuits. The DAC is asynchronous and has programmable A-and Mu-255 law PCM conversion capability. Coupled directly to the C DAC is an operational amplifier receive filter circuit which utilizes the C DAC as an input capacitor thereby eliminating the need for a buffer amplifier and allowing the DAC to be used for both analog to digital and digital to analog conversion.

Multiple function operational amplifier circuit

A temperature stable bandgap voltage reference source utilizing bipolar transistors biased at different emitter current densities is provided. Switched capacitors are used to input the V.sub.be and the .DELTA.V.sub.be of the transistors (PTC and NTC voltages, respectively,) into an operational amplifier to provide a reference voltage proportional to the sum of the PTC and NTC voltages. Proper selection of the ratio of the switched capacitors renders the reference voltage substantially independent of temperature. In a modified form of the reference, the reference amplifier is implemented by an auto-zeroed operational amplifier which uses switched capacitor techniques and an integrated capacitor to achieve the auto-zeroing function.

Auto-zeroing operational amplifier circuit

A companded stacked DAC is provided which can be used in an A-law or .mu.-law conversion merely by selection. The companded DAC is inherently monotonic and can be integrated with field effect transistors. The current sources of the DAC are switched to only one of two buses. The stacked DAC includes a chord DAC and a step DAC. The two buses which the chord DAC is connected to are maintained at approximately equal voltages by the use of a reference amplifier. The companded DAC uses successive approximation when converting.

Programmable A-law and .mu.-law DAC

A single chip MOS regulated negative power supply is comprised of first, second and third strings of field effect transistors and first and second amplifiers. The first string in conjunction with the zener diode develops a reference voltage which then passes through a voltage to current converter comprised of a first amplifier, the second string and an output transistor. The current thus produced passes through a third string of field effect transistors which is referenced to ground. The second amplifier provides negative feedback to the third string to produce the regulated output.

Regulated negative voltage supply

A CMOS circuit having high voltage capability is provided. At least one P channel transistor is coupled between a first voltage node and an output of the circuit. At least two N channel transistors are coupled in series between the output of the circuit and a second voltage node. The at least two N channel transistors each have a separate tub which is connected to the source of each respective N channel transistor. This arrangement of the N channel transistors provides at least one tub which is isolated from the voltage nodes when the output of the circuit is at a potential substantially equal to a voltage present at the first voltage node.

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Austin, TX, United States of America

Richard W Ulmer