Gte Laboratories Incorporated

Richard W Sieber

Michael Cooperman

Arnold Paige

Donald J Gray

Rob Moolenbeek

Phillip Andrade

Lalit Patel

Shou-I Wang

David A Perreault

Arnold H Bearak

A distributed switch buffer and method for switch buffer enlargement use standard switch chips as modules that are cascaded in multiples to provide arbitrarily large switch buffers for any number of inputs and outputs. Any type of packet switch chip may be used in any combination. A packet that enters the first switch chip in the cascade automatically gets transferred to other switch chips as part of an integrated buffering scheme. Every input of the switch is connected to all of the switch chips in the first stage of the distributed buffer. The queue of each output of the switch is then expanded by adding more stages of switch chips. All outputs of each switch chip go to the inputs of the same switch chip in the next stage of the distributed buffer so that all of the buffer space of all the cascaded switch chips is available to each input port. The queue may be expanded indefinitely by cascading more chips. In one embodiment, inputs are connected to all the cascaded switch chips for each output port so that each chip only needs to have one output. The number of inputs for each switch chip in the intermediate stages need not equal the number of outputs from that stage, and it is possible to use a different number of cascade stages for each switch output port.

Distributed switch buffer utilizing cascaded modular switch chips

An asynchronous transfer mode switch with shared memory under the control of a content addressable memory, receives serially through a plurality of input ports a plurality of cells of digital data packets during a specific time period, each packet having a header. The header of each said cell is processed and temporarily stored. The data bits of each cell are temporarily stored, and transferred in parallel to a random access memory, using available addresses in said random access memory. A header processor assigns an arrival number to each received cell, and extracts the output port destination and priority of each cell from said headers. A content addressable memory stores the arrival number, output destination port and priority of each data cell. A read control provides sequentially, in order of priority, arrival numbers, and destination addresses, to said content addressable memory for determining the order in which cells of data are read from said random access memory. When a match is found in said content addressable memory, the cell of data from the associated address in said random access is read out to its output destination port under control of said content addressable memory.

ATM shared memory switch with content addressing

A broadband space switch matrix includes a parallel combination of individual switch modules each comprising a cascade of pass-transistor selectors, NAND gates, and inverters arranged into a multi-stage tree multiplexing configuration. The switching speed is increased by isolating each switching crosspoint from the stray capacitive loading in the matrix.

Broadband switch

Electrical circuitry of CMOS inverter circuits in cascade providing a compatible interface between ECL logic levels and CMOS logic levels. The ECL input is applied to the gate of the N-type transistor of the first inverter circuit. A threshold control circuit includes a CMOS inverter circuit with the gate of the N-type transistor connected to a reference voltage and the gate of the P-type transistor connected to its drain is connected to the gate of the P-type transistor of the first inverter circuit. The threshold control circuit adjusts the threshold voltage of the first inverter circuit so as to compensate for changes in current flow through the N-type or P-type transistors, thereby permitting operation over extreme variations in circuit parameters under situations of poor operating tolerances and wide temperature variations.

Electrical circuitry with threshold control

A broadband space switch matrix constructed from a plurality of NAND gates arranged into a set of cascaded stages to form a tree-switch multiplexing configuration. A plurality of input digital signals are applied to input ports coupled to the NAND gates in the first stage. A selected one of the input signals emerges as an output signal from an output port coupled to a single NAND gate in the last stage. Each NAND gate has a select line for receiving control signals. The switching path for the selected input signal is established by placing the sequence of NAND gates defined by the selected switching path in a state of conduction whereby only the selected input signal propagates through the switch. This is effected by forcing to a HIGH state the particular NAND gates in each stage whose outputs are coupled to the same NAND gate in the following stage along with the output of the NAND gate in the current stage which is in the chosen path. The forced HIGH state is achieved by applying a LOW state signal to the respective select lines of the particular NAND gates. In an alternate arrangement, the NAND gates in the first stage are replaced by 2:1 pass-transistor-selectors which offer a reduction in the number of transistors.

Broadband switch using deactivated crosspoints for establishing

A broadband space tree-switch matrix establishes a desired switching path by sensitizing only the sequence of logic gates defined by the desired path such that only these sensitized logic gates are operable to undergo switching and thereby permit transmission of only the corresponding input signal. The tree-switch includes a plurality of cascaded stages wherein the first stage consists of dual-input NAND gates each receiving a corresponding input signal at one input and a control signal at another input. The remaining stages include a plurality of switching nodes each having a first NAND gate cascaded to a second NAND gate wherein the second NAND gate has a HIGH steady-state logic signal present at one of its inputs. An appropriate combination of control signals are applied to the NAND gates in the first stage to effect a selected switching path. A second broadband space switch matrix comprises a plurality of NAND gates arranged into a series of cascaded stages to form a tree-switch configuration. The first and second stages include equal numbers of NAND gates corresponding to the number of input signals. Furthermore, the NAND gates in only the first and second stages each have a control input for receiving control signals to establish a selected path. The tree-switch likewise operates to sensitize a particular path in response to the control signals so that only the NAND gates in the selected path are operable to undergo switching.

Broadband tree switch architecture for reducing pulse width narrowing

A broadband switching matrix having M.times.N crosspoint switches is arranged into a selected number of groups of vertically cascaded stages in which adjacent groups are interconnected with expansion stages. An input signal switched from row to column in a particular group propagates through the remaining stages in that group and then propagates successively through the expansion stages in each following group before reaching an output port. In another array configuration, a set of N multiplexers arranged in parallel each receive N input signals and provide a single output signal at a respective output port. The multiplexers are constructed from 2:1 selector elements which are arranged in a vertical tree configuration having log.sub.2 N cascaded stages. Each multiplexer has the same number of stages and hence selector elements. Both broadband switching arrays are designed so that each switch drives only one other switch in the array, thereby minimizing capacitive loading and maximizing propagation speed.

Broadband switch matrix with non-linear cascading

Electrical circuitry providing a compatible interface between ECL logic level of -1.6 and -0.8 volts and CMOS logic levels of 0 and +5 volts. Voltage sources of -3.7 and +1.3 volts are provided for supplying operating voltages to the CMOS circuitry in order to set the threshold voltage CMOS inverters at -1.2 volts, the threshold voltage of ECL logic circuits.

Electrical circuitry providing compatibility between different logic

A broadband switching array for equalizing the delay experienced by input signals as they propagate through their respective swtiching hpaths, and for providing output signals having uniform logical polarities. A cascaded set of delay means is connected to each of the input ports of the array in accordance with the amount of additional delay that is needed to accomplish equalization. Likewise, a cascaded set of inverter means is connected to each ouput port so that each switching path performs a common number of inversion operations, thereby allowing the output signals to have the same logical polarity.

Broadband switching matrix for delay equalization and elimination of

A system for transmitting digital signals over a transmission line including a driver of an inverter employing CMOS FET's and a termination of an inverter employing CMOS FET's. A sense/control circuit at the termination senses changes in the operating condition of the driver inverter and in response thereto controls the operating condition of the termination inverter. Under steady state conditions the termination inverter establishes the appropriate voltage at an output connection coupled thereto without dissipating any power.

Bidirectional digital signal transmission system

A crosspoint switching array of a matrix of crosspoint switches connected in rows and columns. Each crosspoint switch includes an MOS inverter circuit for propagating a digital signal from crosspoint-to-crosspoint along its row. Each crosspoint switch includes a first MOS switch connected to the preceding crosspoint switch in the column and a second MOS switch connected to its row. The second switch is activated to connect the row to the column at a particular crosspoint. Otherwise, the first switch is activated to connect the crosspoint switch to the preceding crosspoint switch in the column. The output of the first or second switch is applied to an MOS inverter circuit for driving the following crosspoint switch in the column.

Crosspoint switching array

In a digital communication system including a central PABX subsystem coupled by a transmission line to a remote telephone subsystem, a method for establishing synchronization between the PABX and the telephone. The data format includes a message transmitted from the PABX to the telephone during the first half of a frame and a response transmitted from the telephone to the PABX during the second half of the frame. The synchronization method includes the steps of recognizing that synchronization has been lost, discontinuing transmission of responses by placing the line driver in a high impedance state while continuing transmission of messages, and detecting a valid message on the transmission line. The valid message is detected by finding in sequence, a message stop bit, the stop bit remaining on the line for one half frame and a message start bit. When a valid message is detected, transmission of responses is resumed.

Method for synchronizing a digital communication system

In a data transmission system including a central subsystem coupled by transmission lines of different lengths to a plurality of remote subsystems, methods and apparatus for synchronizing responses to messages transmitted by the central subsystem to compensate for different line delays are provided. The messages are transmitted by the central subsystem during the first portion of a frame, while the responses are transmitted by the remote subsystems during a second portion of the frame. In each of the remote subsystems, a compensation delay equal to a maximum line delay associated with the longest of the transmission lines less an actual line delay associated with the transmission line connected to that remote subsystem is determined. The response to the message is then delayed by the compensation delay so that the responses from each remote subsystem arrive at the central subsystem delayed by the maximum time delay. The central subsystem detects the response during a detection interval delayed by the maximum time delay after the end of the message.

Line delay compensation for digital transmission systems utilizing low

A digital switching system is described for providing time division multiplexed digital communication of parallel sequential signals of N words each of M bit length between N telephone data subscribers over N transmission lines in which an array of orthogonal RAM memory devices provide parallel-to-serial conversion and multiplexing of the N words each of M bit length to provide a time division multiplexed serial digital bit stream of M words, each N bits in length, which are transmitted over a transmission line to a serial-to-parallel converter and coupled to a second orthogonal RAM memory device in which the N words M bits in length from the serial-to-parallel converter are stored and coupled to N telephone data subscribers over the transmission lines.

Digital switching system with two-directional addressing rams

A digital switching system for switching messages between a plurality of subscribers located a relatively short distance from the switching system. The message format for the system comprises the serial transmission of messages of M bits of information which are transmitted from the switching system to the subscribers during one-half of a transmission frame and messages of M bits of information which are transmitted from the subscribers to the switching system during the other half of the transmission format. Addressable memory arrays are employed at the switching system for multiplexing and serial-to-parallel conversion and switching. In a preferred embodiment up to 40 telephone and/or data terminal messages are handled in 125 microsecond time frames with 8 bit voice and 8 bit data words plus a start and stop bit and 1 signalling bit message format from each of the subscribers.

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Attleboro, MA, United States of America

Richard W Sieber