International Business Machines Corporation

Richard W Noth

John Gow, 3rd

Gordon A Kelley, Jr

Edward John Dombroski

William H Guthrie

Herman S Hoffman

Kurt Hinrichsmeyer

Werner Straehle

Floyd R Moser

James A Bilowith

A compliant lead for electromechanically surface mounting an integrated circuit chip package to a substrate. The compliant lead extends from the package and includes at least two regions of different lead thickness. In a first region, a standard lead thickness is employed to ensure the applicability of existing package fabrication techniques. A second region, having a reduced thickness, then extends from the first region and is predefined to encompass an area of the lead expected to undergo greatest stress during thermal cycling. Compliancy is further guaranteed by providing a solder dam within the region of reduced thickness to limit wicking of solder when the package is solder mounted to the substrate. Lead frame fabrication is also discussed.

Compliant lead for surface mounting a chip package to a substrate

An improved package for semiconductor chips, and method of forming the package are provided. The package includes a lead frame having a central chip bonding portion and first and second sets of interdigitaled fingers. The inner ends of the first set of fingers terminate at a distance from the central chip bonding portion closer than the inner ends of the fingers of the second set at fingers. A semiconductor chip, having input/output pads is bonded to the central chip bonding portion. A first set of wires directly couples respective input/output pads on the chip to the first set of fingers. A second set of wires couples respective input/output pads on the chip with the second set of fingers. Each of the wires of the second set of wires has a first segment extending from its respective input/output pad to an intermediate bonding region, and a second segment extending from the intermediate bonding region to its respective finger of the second set of fingers.

Lead frame-chip package with improved configuration

According to the present invention, an improved chip and leadframe package assembly and method of making the same is provided. The package assembly is comprised of a metal leadframe having a chip bond pedestal centrally located and a plurality of discrete leads surrounding the pedestal. An I/C (integrated circuit) semiconductor chip is mounted on the pedestal, the chip having a plurality of connection or bonding pads disposed around the periphery. An interposer having a layer of dielectric material and discrete metal lines formed thereon is mounted on an apron of the chip bonding pedestal between the location of the chip and the inner discrete leads of the leadframe. Connections are provided between the bonding pads on the chip and the respective lines on the interposer and connections are also provided between the fingers and the respective lines on the leadframe. Additionally, the interposer also preferably includes at least one voltage bus line formed thereon having a portion adjacent at least one edge of the chip for connection of any of the chip bond pads thereto. Further, the pedestal also preferably includes radially extending conducting arms suitable for providing both electrical ground connection and a heat dissipation path.

High performance versatile thermally enhanced IC chip mounting

A semiconductor package utilizing a carrier with substantially parallel top and bottom surfaces having a recess in the bottom surface and a slot in the top surface communicating with the recess in the bottom surface and provided with electrical conductors on its top surface is provided with an integrated semiconductor chip having a major surface and contact pads on the major surface in the recess of the carrier, with said contact pads positioned in the region of said slot so that the contact pads can be connected by lead wires passing through said slot, to the conductors on the top side of the carrier. The active surface of the chip containing the contact pads is encapsulated but the back surface of the chip and carrier is left exposed to improve the thermal characteristics of the chip while maintaining a low package profile.

Integrated semiconductor chip package

Multiple, single conductor, tape automated bonding (TAB) tapes are sequentially applied to a semiconductor device by the bonding of a first, etched, single layer TAB tape to an outer row of bonding pads on a semiconductor chip and to selected contacts on a lead frame followed by the laying down of at least one additional etched, single layer TAB tape which is then bonded to an inner row of bonding pads on the semiconductor chip and to different selected lead frame contacts. If desired the subsequent TAB tape may be adhered to the preceding TAB tape to increase the mechanical strength of all the tapes and improve the electrical characteristics of the tapes. The application of one or more ground planes to the assembly is also shown.

Tape bonded semiconductor device

A method of packaging an electronic module in a cap is disclosed. The module, comprising one or more silicon chips mounted on a substrate and having the chips sealed onto the substrate with a silicone polymer is supported on a cap with the chips disposed inwardly. An epoxy is dispensed on the back surface of the substrate and allowed to flow and bridge over the gap between the substrate and cap. The epoxy is cured by first heating the assembly with the applied epoxy to a temperature which will gel the epoxy. The temperature and rate of heating are selected so that the temperature is stabilized before the critical viscosity of the epoxy is reached. Subsequently, a higher temperature is used to complete the cure. The process is also characterized in that no significant decrease in temperature is permitted after the dispensing and flowing of the epoxy.

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Fairfax, VT, United States of America

Richard W Noth