United States of America As Represented by the Secretary of the Air Force

Richard W Linderman

Qing Wu

Yiran Chen

Hai Li

Garrett Rose

Miao Hu

Mark Herron Linderman

Mark D Barnell

Erick A Schlueter

Oinru Qiu

Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems. Invention provides iterative training of memristor crossbar arrays for neural networks by applying voltages corresponding to selected training patterns. Error is detected and measured as a function of the actual response to the training patterns versus the expected response to the training pattern.

Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems

Invention provides an apparatus and method for performing signal processing on a crossbar array of resistive memory devices. The invention is implemented using one or multiple crossbar arrays of resistive memory devices in conjunction with devices for converting input real number representations to voltage waveforms, devices for converting current waveforms into voltage waveforms, and devices for converting voltage waveforms to real numbers outputs.

Method and apparatus for performing signal processing on a crossbar array of resistive memory devices

An apparatus that performs the mathematical matrix-vector multiplication approximation operations using crossbar arrays of resistive memory devices (e.g. memristor, resistive random-access memory, spintronics, etc.). A crossbar array formed by resistive memory devices serves as a memory array that stores the coefficients of a matrix. Combined with input and output analog circuits, the crossbar array system realizes the method of performing matrix-vector multiplication approximation operations with significant performance, area and energy advantages over existing methods and designs. This invention also includes an extended method that realizes the auto-associative neural network recall function using the resistive memory crossbar architecture.

Apparatus for performing matrix vector multiplication approximation using crossbar arrays of resistive memory devices

A method for context-aware text recognition employing two neuromorphic computing models, auto-associative neural network and cogent confabulation. The neural network model performs the character recognition from input image and produces one or more candidates for each character in the text image input. The confabulation models perform the context-aware text extraction and completion, based on the character recognition outputs and the word and sentence knowledge bases.

Method for context aware text recognition

A single Printed Circuit Board (PCB) designed to acquire data from a multiplicity of heterogeneous sources and convert the data to a high performance protocol suitable for transmission over long distances via fiber optic lines. A specific embodiment uses the Fiber Channel protocol on fiber optic cables to carry information between sensors and high performance computers (HPC). The High Performance Parallel Interface (HiPPI) is used as the protocol to connect to the HPC. Simplex (unidirectional) and full duplex communications are supported.

Data transfer interfacing

Chip-like stacks of thinned chips are mounted in wells etched into a substrate. A 'chip-like' stack is a stack of chips, which in the aggregate have a height approximately equal to that of a single conventional chip. These chip-like stacks are mounted in a variety of packages. In a preferred embodiment, the stacks are mounted in wells within the substrate of an integrated circuit and the stack is provided with a patterned overlay so that all the circuit connections can be made from the upper surface of the stack. The patterned overlay is protected by a planar insulator. A plurality of substrates may be stacked, one upon the other.

Density improvement for planar hybrid wafer scale integration

A five-transistor static Random Access Memory (SRAM) cell accessed by a single bitline merged with heterogeneous memories, such as ROMs, EPROMs, EEPROMs, and DRAMs. Combined ROM and RAM cells have been included within a high performance signal processor. Advantages include area and power dissipation savings resulting from shared column bitlines, associated column decoders, and column sense amplifiers. This eliminates circuit duplication.

Shared bitline heterogeneous memory

Chip-like stacks of thinned chips are mounted in wells etched into a substrate. A'chip-like' stack is a stack of chips, which in the aggregate have a height approximately equal to that of a single conventional chip. These chip-like stacks are mounted in a variety of packages. In a preferred embodiment, the stacks are mounted in wells within the substrate of an integrated circuit and the stack is provided with a patterned overlay so that all the circuit connections can be made from the upper surface of the stack. The patterned overlay is protected by a planar insulator. A plurality of substrates may be stacked, one upon the other.

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Rome, NY, United States of America

Richard W Linderman