Adaptec, Inc.

Cisco Technology, Inc.

Lockheed Martin Corporation

Stmicroelectronics Gmbh

Loral Aerospace Corp.

Ford Aerospace Corporation

Pocketscience, Inc.

Lockheed Martin Aerospace Corporation

Wideband Computers, Inc.

Pocketmail Inc.

Richard W Koralek

David H Miller

Steven Lan

Francis James Smith

Gregory G Raleigh

Vincent K Jones

Frank Chethik

Derek Gerlach

Zongbo Chen

Brian D Korek

Richard C Beerman

Wade Langill

Frank S Lee

David Bruce Isaksen

Byron Esten Danzer

Robert M Tanner

Steven Andersen

Michael E Jacobson

James F Lebar

Chris Hinkle

James Berman

James Pressey

Donald R Pandori

Stephen B Lengel

A burst error limiting symbol detector system includes a symbol detector circuit responsive to a corrected sample signal for detecting multilevel or multidimensional symbols encoded in the corrected sample signal with reference to a plurality of associated thresholds. A feedback equalizer circuit provides a feedback equalizer signal for cancelling undesired distortion in an input signal. A summing circuit is responsive to the input signal and the feedback equalizer signal to provide the corrected sample signal to the symbol detector circuit. A feedback modification circuit is responsive to the corrected sample being within one of a plurality of valid symbol windows to feed back the detected symbol to the feedback equalizer and is responsive to the corrected sample being within one of plurality of marginal threshold windows to feed back a corresponding intermediate value to the feedback equalizer.

Burst error limiting feedback equalizer system and method for multidimensional modulation systems

A modular Galois-field subfield-power integrated inverter-multiplier circuit that may be used to perform Galois-field division over GF(245). The integrated inverter-multiplier circuit combines subfield-power and parallel multiplication and inversion operations performed therein. The circuit is modular, has a relatively low gate count, and is easily pipelined because it does not use random logic. The circuit implements mathematical calculations known as 'Galois-field arithmetic' that are required for a variety of digital signaling and processing applications such as Reed-Solomon and Bose-Chaudhuri-Hochquenghem (BCH) error-correction coding systems. Galois-field division is particularly difficult, typically requiring either a great deal of time or highly complex circuits, or both. The circuit uses a unique combination of subfield and power inversion techniques to carry out multiplicative inversion. Furthermore, the circuit uniquely implements Galois-field division by carrying out the multiplicative inversion and the multiplication simultaneously and in parallel. This substantially increases computation speed. The modularity and pipelineability of the present invention also make system design easier and increases the speed and reduces the gate count of an integrated circuit embodying the inverter-multiplier circuit.

Modular Galois-field subfield-power integrated inverter-multiplier circuit for Galois-field division over GF(256)

Systems and methods for augmenting the performance of iterative soft decision-in soft decision-out decoding of block codes with extrinsic information based on multiple parity equations inherent to the block codes. Cyclic shifting of codewords may be applied in the context of iterative soft decision-in soft decision-out decoding to maximize the usefulness of a parity equation corresponding to any particular codeword bit. Soft decisions are determined on a bit-by-bit basis in response to multi-bit symbol measurements. This allows the use of relatively inexpensive bit-based decoders for decoding of multi-bit symbols.

Iterated soft-decision decoding of block codes

The present invention uses an acoustic modem embedded in a remote device enhanced with automatic repeat request and forward error correction routines to provide reliable transfer of electronic messages from the messaging server to the remote device. This may provide significantly better error correction than standard PC modems. Also the present invention, may provide a fast, reliable connection sequence by use of a preamble frame. According to an embodiment of the present invention, a method of communicating messages between a messaging server and a remote device is provided. The method includes a variety of steps such as establishing a connection between the messaging server and the remote communication device by transmitting a preamble frame, exchanging data frames between the remote device and the messaging server, detecting and correcting errors in received frames, and re-transmitting received frames, if errors are uncorrectable.

Messaging communication protocol

A timing recovery system and method for QAM signals having different symbol rates are disclosed. After sampling the QAM baseband signal, a symbol timing recovery logic including a generator of a weighting function is utilized to develop a local error signal. The local error signal averaged over a predetermined time period is utilized to make a global decision regarding the sampling point position relative to the baseband signal maximum/minimum.

Timing recovery circuit in QAM modems

An integrated circuit for error correction takes advantage of a novel data representation ('tower representation') for a selected finite Galois field. Using this representation, novel circuits which utilize the hierarchical structures in the subfields of the selected finite Galois field can be constructed. In one embodiment, GF(256) multipliers, GF(256) multiplicative inverse circuits, GF(256) logarithm circuits can be constructed out of GF(16) multipliers, GF(16) multiplicative inverse circuits and other GF(16) components. These GF(16) components, in turn, can be constructed from still simpler GF(4) components. In that embodiment, a user-programmable burstlimiter is provided. In that embodiment also, a novel quadratic equation solver is provided.

Arithmetic logic unit and method for numerical computations in Galois

Improvements to amplitude phased keyed digital communications systems and to the processing of amplitude phase keyed symbols transmitted over radio frequency channels. The present invention provides for an amplitude phased keyed digital communications system including an adaptive baseband equalizer, a digital symbol recovery circuit in accordance with the present invention, and a quadrature demodulator. The adaptive baseband equalizer receives amplitude phased keyed signals and outputs in-phase and quadrature digital amplitude values corresponding to the received amplitude phased keyed signals. The digital symbol recovery circuit comprises a programmable addressable random access memory that stores a plurality of eight bit words comprising decoded symbol sets of the received amplitude phased keyed signals, and outputs the decoded symbol sets in response to addresses corresponding to the in-phase and quadrature output signals. The quadrature demodulator processes the decoded symbol sets and outputs recovered amplitude phased keyed symbols corresponding to the received amplitude phased keyed signals. Eight bit I and Q amplitude values address 256.times.256 memory locations in the memory of the digital symbol recovery circuit. For example, at each memory location, a seven bit word, for example, is stored. The first four bits define a 4-tuple for the decoded symbol. The fifth bit is a bang-bang phase bit or carrier tracking bit. The sixth bit is a bang-bang automatic gain control bit. The seventh bit is a false lock indicator bit.

Adaptive digital symbol recovery for amplitude phased keyed digital

A circuit and method includes a global parity symbol in a multi-way interleaved Reed-Solomon code implementation to enhance error-detection capability of the Reed-Solomon code. In one embodiment, the global parity symbol is computed over both the data symbols and the check symbols of the Reed-Solomon code, thereby providing data detection capability for errors occurring in the check symbols.

Global parity symbol for interleaved reed-solomon coded data

Arithmetic logic unit and method for numerical computations in galois

System and method for encoding and decoding data using numerical

System and method for solving quadratic equation in galois fields

An equalizer that mitigates both linear and nonlinear distortions for amplitude phase keyed signals that are processed thereby. Algorithms employed in the equalizer are based on correcting received signals based on symbol transitions between successive symbols. The linear portion of the equalizer is programmable and can use any available algorithm. Programmable linear taps of the equalizer may be programmed in a nonlinear manner by using the lookup tables as amplitude dependent equalizers that are used to process one symbol at a time. In the equalizer, each amplitude level has it's own correction factor by using amplitude dependent coefficients. The equalizer can implement both linear and nonlinear equalization. Equalizer corrections are implemented using predetermined values stored in lookup tables. The equalization corrections are determined in an external computer and are loaded into the lookup tables for each amplitude level of the received signals. The equalizer is programmable and may be used with any amplitude phase keyed signal by reprogramming the lookup tables from the external computer for the desired modulation.

Programmable digital linear and nonlinear transversal equalizer

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Palo Alto, CA, United States of America

Richard W Koralek