National Semiconductor Corporation

Richard W Foote, Jr

Rodney L Hill

William Max Coppock

Victor Torres

Terry Lee Lines

Tom Bold

Sandeep Raj Bahl

Charles A Dark

Darren Lee Rust

A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.

Ohmic contact schemes for group III-V devices having a two-dimensional electron gas layer

An efficient method is disclosed for creating different field oxide profiles in a local oxidation of silicon process (LOCOS process). The method comprises (1) forming a first portion of the field oxide with a first field oxide profile (e.g., an abrupt bird's beak profile) during a field oxide oxidation process, and (2) forming a second portion of the field oxide with a second field oxide profile (e.g., a graded bird's beak profile) during the field oxide oxidation process. A graded bird's beak profile enables higher breakdown voltages. An abrupt bird's beak profile enables higher packing densities. The method gives an integrated circuit designer the flexibility to create an appropriate field oxide profile at a desired location.

System and method for creating different field oxide profiles in a locos process

A buried thin film resistor having end caps defined by a dielectric mask is disclosed. A thin film resistor is formed on an integrated circuit substrate. A resistor protect layer is formed over the thin film resistor. A layer of dielectric material is formed over the resistor protect layer. The dielectric material is masked and dry etched to leave a first portion of dielectric material over a first end of the thin film resistor and a second portion of dielectric material over a second end of the thin film resistor. The resistor protect layer is then wet etched using the first and second portions of the dielectric material as a hard mask. Then a second dielectric layer is deposited and vias are etched down to the underlying portions of the resistor protect layer.

System and method for providing a buried thin film resistor having end caps defined by a dielectric mask

A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the emitter resistance of the transistor device are related to the thickness of the interfacial oxide layer. The oxide of the interfacial oxide layer is grown in a low pressure, low temperature pure oxygen (O) environment that greatly reduces the oxidation rate. The low oxidation rate allows the thickness of the interfacial oxide layer to be precisely controlled and sources of variation to be minimized in the manufacturing process.

System and method for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor

A system and method is disclosed for providing an etch procedure to facet the top corners of a via in a semiconductor device. A vertical anisotropic dry etch process is applied through an aperture in a resist mask to etch through a dielectric layer down to a bottom conductor layer. The resist mask is removed and an etch process is applied to etch away corner portions of the dielectric layer. The etch process forms a flat sidewall surface in the portions of the dielectric layer that form the via. The flat sidewall surface is disposed at an obtuse angle with respect to the top surface of the dielectric layer and at an obtuse angle with respect to a vertical sidewall of the via cavity. The flat sidewall surface and the absence of sharp corners facilitate a subsequent metal fill process.

Growing community of inventors

Kennedale, TX, United States of America

Richard W Foote, Jr