International Business Machines Corporation

Morton International, Inc.

Microcoating Technologies, Inc.

Other

Richard W Carpenter

Andrew Tye Hunt

Wen-Yi Lin

Christina Marie Boyko

Shara S Shoup

Krystyna Waleria Semkow

Raymond Thomas Galasco

Tzyy Jiuan Hwang

Michelle Hendrick

Stephen E Bottomley

Herbert Wegener

Voya Rista Markovich

David W Wang

William J Summa

Joseph Gene Sabia

Robert E Ruane

Peter J Lueck

Cindy M Reidsema

Francis J Bucek

Darleen Mayo

Edward J Bonafino

Wayne E Nacker

Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material and layers of dielectric material. Outer resistive material layers are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material on opposite sides of the laminate act as capacitors. Electrical pathways horizontally through resistive material layers, which may be connected by via plated holes, act as resistors.

Nanolaminated thin film circuitry materials

A method is provided for forming a patterned layer of resistive material in electrical contact with a layer of electrically conducting material. A three-layer structure is formed which comprises a metal conductive layer, an intermediate layer formed of material which is degradable by a chemical etchant, and a layer of resistive material of sufficient porosity such that the chemical etchant for said intermediate layer may seep through the resistive material and chemically degrade said intermediate layer so that the resistive material may be ablated from said conductive layer wherever the intermediate layer is chemically degraded. A patterned photoresist layer is formed on the resistive material layer. The resistive material layer is exposed to the chemical etchant for said intermediate layer so that the etchant seeps through the porous resistive material layer and degrades the intermediate layer. Then, portions of the resistive material layer are ablated away wherever the intermediate layer has been degraded.

Formation of thin film resistors

To form thin film electrical components, a thin film having desired electrical properties is deposited on a substrate of dissimilar material. Thermal energy from a computer guided laser is used to remove selected portions of the thin film. In accordance with one aspect of the invention, the thin film is an electrically conducting material, such as platinum or doped platinum, and the substrate is metal foil, such as copper foil. The thermal energy from the laser ablates away portions of the thin film. In accordance with another aspect of the invention, a layer of zero valence metal is deposited on a dielectric material substrate which has a melting point or decomposition temperature substantially above that of the zero valence metal. The zero valence metal layer is patterned to form electronic circuitry components by computer guided laser which provides sufficient thermal energy to boil away selected portions of the zero valence metal layer. In one preferred embodiment, electronic circuitry is formed from a three-layer composite comprising nickel foil; a dielectric material, such as silica deposited on the foil; and a zinc layer deposited on the dielectric material. The zinc layer, having a boiling point substantially below the melting points of the dielectric material and the nickel foil, is patterned by laser-derived thermal energy.

Laser imaging of thin layer electronic circuitry material

A thin electrical circuitry structure is formed which contains conductive circuitry traces, integral capacitors and integral resistors. A first laminate structure comprises a conductive foil having a layer of embeddable dielectric material laminated thereto. A second laminate structure comprises a conductive foil having a layer of resistive material on one side, the thickness of the resistive material layer being less than that of the layer of embeddable dielectric material. The resistive material layer is circuitized to produce resistive patches, and the two structures are laminated together, embedding the resistive patches in the dielectric material layer. One of the foils is circuitized providing circuitry traces, optional inductor coils, and capacitor plates. That foil embedded in dielectric laminate to support the structure for further processing. The other foil is then circuitized providing circuitry traces, optional inductor coils and capacitor plates. Traces on one side connector with the resistive material patches to provide the resistors.

Thin integral resistor/capacitor/inductor package, method of manufacture

To secure a thin film to a rigid carrier for subsequent exposure to processing chemicals, the thin film is initially adhered to the rigid carrier with a light adhesive from which the thin film may later be peeled. Then a photoresist is applied over the thin film extending over a peripheral region of the carrier along the perimeter of the thin film. The photoresist is exposed to actinic radiation in a pattern such that when the photoresist is subsequently developed, a perimeter region of the photoresist remains over the perimeter region of the carrier and extending inward over the periphery of the thin film sufficiently to secure the thin film during conveyorized chemical processing. Finally the resist is stripped to release the thin film and the thin film pealed from the adhesive pattern.

Method for securing and processing thin film materials

Resistors are formed by selective etching from layered thin film material comprising an insulating substrate, a resistive material which is a mixture of a zero valence metal and a dielectric material, and a layer of conductive material.

Deposition of resistor materials directly on insulating substrates

A process for connecting at least two electrically conductive patterns through a dielectric material by a landless electrical connection is provided. The process includes providing a composite containing a dielectric substrate having a conductive plane on at least one of its major surfaces and a temporary support layer covering the conductive plane. Blind vias are provided in the dielectric substrate and are plated with an electrically conductive material. The temporary support layer is removed thereby providing a landless electrical connection through the dielectric material and the conductive plane is available for providing external electrical conductive pattern.

Process for providing a landless via connection

The present invention relates to a method for selectively electroetching a metal from an electrical device having the steps of: immersing the electrical device in an etching solution; immersing a cathode in the etching solution; applying an etching potential to a preselected area of the metal; and maintaining a passivation potential at the metal to remain unetched. The metal to remain unetched is not electrically connected to the preselected area and the passivation potential does not equal the etching potential. The present invention further relates to a method of forming an electrical connection to the inner layers of a multilayer circuit board having a copper foil surface layer and copper containing inner layers.

Method for forming electrical connection to the inner layers of a

The present invention provides an improved circuit board for mounting integrated circuit chips and a technique for manufacturing the circuit board. The board permits direct chip attachment to the circuit board by providing the necessary geometry for the footprint pattern of the chip connections without the necessity of multi-level packaging using chip carriers. The circuit board includes a substrate with plated through holes, and a film of photoresist dielectric material disposed on the substrate. The dielectric material is photo patterned to form vias which are then filled with conductive material. Electrical connection pads are formed on the exposed surface of the film of dielectric material in the pattern of the chip footprint to be mounted thereon. The vias and plated through holes are arranged in groups and patterns which provide some direct connection between the pads and plated through holes, some pads wired to vias on the exposed surface of the film of dielectric material and some vias wired to plated through holes on the surface of the substrate.

Printed circuit board with aligned connections and method of making same

Selective electroetch of copper and other metals

Disclosed are an electronic package and electronic package module. The module has a dielectric core with surface circuitization on at least one surface. The dielectric core is a composite having a thermoplastic layer interposed between two separate layers of thermoset adhesive, as epoxy dicyanate adhesive. The thermoplastic layer is preferably a polyimide. The adhesive is preferably an epoxy or dicyanate adhesive, for example a homogeneous film of thermoset resin, or a fiber reinforced thermoset resin, such as a polytetrafluorethylene reinforced epoxy or a glass fiber reinforced adhesive. The use of a thermoplastic polyimide layer interposed between adhesive layers provides a core that is particularly amenable to manufacture as a thin core.

Growing community of inventors

Johnson City, NY, United States of America

Richard W Carpenter