Hitachi Micro Systems, Inc.

Elster Electricity, LLC

Richard W Blasco

Chandravadan N Patel

Hiromitsu Inada

Atsushi Kiuchi

Rodney C Hemminger

Scott T Holdsclaw

Edward John Beroset

Tony J Chiang

Peter W Heuell

Valentin Suta

Stig Leira

Basant Khaitan

Konstantin Zh Lobastov

Tahir Sheikh

Shieh C Chen

Kenneth M Chan

The phase shift in an electronic energy meter is compensated for by obtaining temperature and frequency readings in the meter and using these readings in a digital signal processor (DSP) residing within the electronic energy meter. The frequency and temperature compensation is performed to each phase calibration and the result is stored in the DSP. To reduce the possible influence of noise in the system, the compensated DSP values are filtered to provide a smoothing of the data.

System and method for digitally compensating frequency and temperature induced errors in amplitude and phase shift in current sensing of electronic energy meters

A device for simultaneous data input and output and program execution support in digital processors is disclosed. The device includes a plurality of controllable input and output ports for inputting and outputting data from the device, a data cache memory which is selectively couplable to each of the plurality of input and output ports, and a controller for controlling the plurality of input and output ports and the data cache memory. The connectivity and controlablity provided by the present invention effectuates a transfer of data between any of the plurality of input and output ports or the data cache memory. The device provides multiport high-speed and high-throughput non-multiplexed data input and output while maintaining the speed and throughput characteristics of the digital processor because the input/output data transfer takes place simultaneously with digital processor program execution. The processor need not wait for data transfers from external data sources when this device is used. The non-multiplexed multiport configuration further allows data sources of different types, such as serial, parallel, and direct memory access, to be simultaneously connected to the device.

Device for simultaneous data input/output and execution support in

A memory buffer for buffering data from an external memory to a processor including a cache memory, a first-in-first-out memory, a direct data path, a writing selector for writing data from the external memory to one of the cache memory, first-in-first-out memory and direct data path, a reading selector for reading data from one of the cache memory, first-in-first-out memory and direct data path and a controller for controlling the writing and reading selectors in response to the occurrence of certain conditions.

Instruction cache buffer with program-flow control

A device for multi-precision and block arithmetic support in a digital processor including a multiplier for multiplying two signed, unsigned or signed and unsigned binary numbers and having a dynamic range greater than -1 to +1, an arithmetic and logic unit for performing arithmetic and logic operations, a barrel shifter for barrel shifting at least one binary number, shifters for selectively shifting the output of the multiplier and multiplexers for selecting and interconnecting the outputs and inputs of the multiplier, the arithmetic and logic unit, the barrel shifter and the shifters.

Device for multi-precision and block arithmetic support in digital

A digital peak and valley detector including a peak value address register, a valley value address register, a peak value data register, a valley value data register, a peak comparator for comparing the value stored in the peak value data register with value data contained in the digital signal applied to the digital peak and valley detector and for causing the greater of the two to be stored in the peak value data register while simultaneously storing the address in the peak value address register and a valley comparator for comparing the valley value contained in the valley value data register with the value data contained in the digital signal applied to the digital peak and valley detector for determining which is less and for causing the value and the address of the smaller of the two to be stored respectively in the valley value data and the valley value address registers.

Digital peak and valley detector

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Auburn, CA, United States of America

Richard W Blasco