Emc IP Holding Company LLC

Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Emc Corporation

Richard Van Gaasbeck

Bruce Alexander Wilford

Vikram Venkataraghavan

Mark Himelstein

Vishwas Durai

Rick Carlson

Todd Wilde

Blair Barnett

Kevin J Rowett

James Yarbrough

Michael W Shapiro

David R Emberson

Shyam Prasad Pillalamarri

Michael Nishimoto

Samir Rajadnya

Grace Ho

Slawomir K Ilnicki

Karthik Ramachandran

Dan Arai

Ramesh Kavanappillil

Shivaji Ganesh

Curtis P Kolovson

Bill Katz

Bruce Wong

Ewald Comhaire

A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.

Multiprocessor system with independent direct access to bulk solid state memory resources

According to one embodiment, a data processing system includes a plurality of processing units, each processing unit having one or more processor cores. The system further includes a plurality of memory roots, each memory root being associated with one of the processing units. Each memory root includes one or more branches and a plurality of memory leaves to store data. Each of the branches is associated with one or more of the memory leaves and to provide access to the data stored therein. The system further includes a memory fabric coupled to each of the branches of each memory root to allow each branch to access data stored in any of the memory leaves associated with any one of remaining branches.

Exabyte-scale data processing system

A method for controlling wear level operations in solid state memory. The method includes receiving a request to write to a memory location identified by a write address of the solid state memory, and making a first determination that the writing to the memory location results in a duplicate write to the memory location. The method further includes, based on the first determination, making a second determination that a number of encountered duplicate writes has reached an adaptively controlled maximum number of duplicate writes, and based on the second determination, performing a wear level operation.

Method and system for adaptive wear leveling in solid state memory

Logical to physical mapping of managed units ('MUs') of object data in a flash memory system storing MUs that are being created continuously by applications running on a client system is maintained in an extent based tree in DRAM for extents of contiguous MUs and in an override tree in DRAM for individual MUs. Extent mapping data in the extent tree for extents comprises a starting address and a length. Mapping data for individual MUs in the override tree comprises individual pointers from logical addresses to physical addresses. Source erase blocks in flash memory are reorganized asynchronously by iteratively moving individual MUs of an object in order from a source erase block to a free erase block to empty the source erase block and free up associated DRAM.

Object based extent mapping for flash memory

Data processing system with a scalable architecture over ethernet

In general, embodiments of the technology relate to a method for storing data. The method includes receiving a request to write data. In response to the request, the method further includes, selecting a first physical address in a first region in a first storage module, selecting a second physical address in a second region in a second storage module, where an amount of wear associated with the first physical address is different than an amount of wear associated with the second physical address, writing a first copy of the data to the first physical address, and writing a second copy of the data to the second physical address.

Method and system for offset mirroring in a storage system

According to one embodiment, a data processing system includes a plurality of processors, each of the processors being coupled to each of remaining processors via a processor interconnect, a plurality of memory controllers, each memory controller corresponding to one of the processors, a plurality of memory targets, each memory target includes one or more branches and a plurality of memory leaves for storing data, and an Ethernet switch fabric coupled to the memory controllers and the memory targets. When a first of the memory controllers writes data to a first of the memory leaves, the first memory controller sends a cache coherence message to remaining ones of the memory controllers to indicate that the data stored in the first memory leaf has been updated, such that any of the remaining memory controllers can update its cache by fetching the data from the first memory leaf.

Non-uniform memory access (NUMA) mechanism for accessing memory with cache coherence

According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.

Flash memory complex with a replication interface to replicate data to another flash memory complex of a data processing system

A page virtualization table (PVT) and one or more block virtualization tables (BVTs) are maintained. The PVT includes PVT entries, each mapping a logical page number (LPN) to a virtual page number (VPN). Each BVT includes BVT entries, each mapping a virtual block number (VBN) to a physical block number (PBN). A request is received for accessing data stored in one of flash memory devices, the request including a first LPN. A search is performed in the PVT based on the first LPN to locate a first PVT entry to obtain a first VPN from the first PVT entry. A search is performed in a first BVT to locate a first BVT entry based on the VPN to obtain a first PBN from the first BVT entry. An input and output (IO) request is issued based on the first PBN to a flash controller associated with a first flash memory device that stores data corresponding to the first PBN.

Software-implemented flash translation layer policies in a data processing system

A method for mitigating the effect of write disturbances in solid state memory. The method includes receiving a request to write to a memory location of the solid state memory, writing to the memory location, identifying a disturbed memory location, identifying a memory region that includes the disturbed memory location, identifying an address, in the memory region, of the disturbed memory location, generating an address hash from the address, and making a first determination that a history of disturbed memory locations in the memory region includes the address hash. The method further includes, based on the first determination, clearing the history of disturbed memory locations, making a second determination that a wear level operation is due, and based on the second determination, performing the wear level operation.

Method and system for mitigating the effect of write and read disturbances in solid state memory regions

A method for recovering storage object records in solid state memory. The method includes, for each memory location of a solid state memory region, reading data fragment metadata and identifying, based on the data fragment metadata, a storage object. The storage object occupies a subset of memory locations of the memory locations of the solid state memory region. The method further includes identifying a first and a last memory location of the subset of memory locations, and restoring a storage object record for the storage object, wherein the storage object record comprises variables that enable a logical to physical address translation for the storage object.

Method and system for recovering storage object records in solid state memory

A method for dynamic write-back cache sizing in solid state memory storage. The method includes receiving a request to write a data fragment to a memory location of a storage medium, identifying a resource required for the writing, and obtaining a state of the resource. The state of the resource is governed by a number of data fragments that are stored in the write-back cache which require the resource. The number of data fragments in the write-back cache which require the resource are limited to enable writing of all data fragments in the write-back cache to the storage medium, within a specified amount of time. The method further includes determining that the state of the resource allows the received data fragment to be stored in the write-back cache, and based on the determination: storing the data fragment in the write-back cache and acknowledging the write request.

Method and system for dynamic write-back cache sizing in solid state memory storage

A method for data migration in solid state memory. The method includes making a first determination that a write limit of a first memory region of the solid state memory has been reached, and based on the first determination: allocating a second memory region in the solid state memory. The method further includes, based on making the first determination: migrating a first data fragment from a first memory location in the first memory region to a corresponding second memory location in the second memory region, updating a migration progress index to include the second memory location, directing future read and write requests that target memory locations included in the migration progress index to the second memory region, and directing future read and write requests that target memory locations not included in the migration progress index to the first memory region.

Method and system for adaptive data migration in solid state memory

A request is received via a message submission queue. The request is sent from a core associated with an external processor coupled by a communication interface. The message submission queue is associated with a memory access engine circuit configured to perform one or more memory access functions. The memory access engine circuit is used to dequeuer a next message from its corresponding message submission queue. The memory access engine circuit is used to perform a message function invoked by the message. The memory access engine circuit is used to receive a result of performing the message function. The memory access engine circuit is used to prepare and send to an external processing core that sent the message a response message determined based at least in part on the result.

Communication between an external processor and FPGA controller

A method for controlling wear level operations in solid state memory. The method includes receiving a request to write to a memory location identified by a write address of the solid state memory, generating a write address hash from the write address, making a first determination that a write history for a memory region includes the write address hash, and based on the first determination: clearing the write history, storing the write address hash in the write history, and making a second determination that a wear level operation is due, and based on the second determination: performing the wear level operation.

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Mountain View, CA, United States of America

Richard Van Gaasbeck