Sifive, Inc.

Richard Van

Wesley Waylon Terpstra

Eric Andrew Gouldey

Huang Chao Wei

Systems and methods for data storage in a non-inclusive cache. An integrated circuit includes a cache that includes a databank with multiple entries configured to store respective cache lines and an array of cache tags. Each cache tag includes a data pointer that points to an entry in the databank. A method includes allocating the entry in the databank to the cache including the array of cache tags from amongst multiple caches in the integrated circuit by writing the data pointer to the cache tag in the array of cache tags.

Data storage in non-inclusive cache

Systems and methods are described to collect latency data of transactions traversing a processor using a performance monitor, which uses a bucket timer based on a granule value in a configurable granule counter. The monitor can determine a transaction time for a transaction, which can then be compared to enumerated buckets (where the bucket size is based on the granule value), determine the appropriate bucket, and increment a latency counter associated with the bucket. The monitor can include a saturation mechanism to account for overflow or saturation. The collected data can be read by an external device to generate a histogram to identify potential problems in the processor or processor pipeline.

Selectable granularity performance monitor

Systems and methods are disclosed for concurrent support for multiple cache inclusivity schemes using low priority evict operations. For example, some methods may include, receiving a first eviction message having a lower priority than probe messages from a first inner cache; receiving a second eviction message having a higher priority than probe messages from a second inner cache; transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy; and, transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.

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San Jose, CA, United States of America

Richard Van