Atmel Corporation

Artemis Acquisition LLC

Richard V De Caro

Danut Manea

Stephen Trinh

Yongliang Wang

Paul Hill

Daniel Harfert

Systems, methods, circuits, devices and computer-readable mediums for configuring serial devices are disclosed. In some implementations, a device comprises: an input for receiving first and second requests from a serial bus; a decoder coupled to the input and configured to determine if either of the first and second requests is a configuration mode request; a controller coupled to the decoder and configured to: in response to a determination that the first request is a configuration mode request, program a configuration block with configuration data obtained from the serial bus and alter a device behavior according to the configuration data; and in response to a determination that the second request is not a configuration mode request, perform one or more actions on the device according to the second request.

Serial device with configuration mode for changing device behavior

A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.

Ultra-deep power-down mode for memory devices

This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

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El Dorado Hills, CA, United States of America

Richard V De Caro