Apple Inc.

Amazon Technologies, Inc.

Elwha LLC

Richard Thomas Witek

Peter C Eastty

Maya Suresh

Long Li

Lowell L Wood, Jr

Roderick A Hyde

Clarence T Tegreene

Jordin T Kare

Nathan P Myhrvold

Muriel Y Ishikawa

Victoria Y H Wood

Thomas A Weaver

William Henry Gates, Iii

Douglas Christopher Burger

Andrew F Glew

Craig J Mundie

Burton Jordan Smith

Rajarshi Mukherjee

John L Manferdelli

Thomas M McWilliams

Brian D Clark

A processor may include a plurality of data memories storing operands that may be operated upon by the processor. Load/store operations may specify a memory location in one of the data memories to be accessed using a memory select value that selects the data memory and an address within the selected data memory. The memory select values may be mapped from virtual memory select values associated with the load/store operations to physical memory select values that may be used to access the data memory.

Memory select register to simplify operand mapping in subroutines

A hardware scheduling circuit may receive priority indications for a plurality of threads for processing, by an execution unit, multiple data samples associated with a signal. A particular thread of the plurality of threads may be scheduled for execution by the execution unit based on a priority of the particular thread and based on an availability of some of the multiple data samples that are to be processed by the particular thread.

System for scheduling threads for execution

In various embodiments, a floating-point arithmetic circuit includes a range exception detection circuit and an output circuit. The range exception detection circuit may generate a selection signal that indicates whether a floating-point arithmetic result generated within the floating-point arithmetic circuit is within a specified range. The output circuit may output the floating-point arithmetic result in response to the selection signal indicating the floating-point arithmetic result is within a specified range. The output circuit may output a corresponding specified value in response to the selection signal indicating the floating-point arithmetic result is not within the specified range. Accordingly, floating-point arithmetic operations may be performed in combination with an operation that limits a range of an output to a specified range.

Floating-point arithmetic operation range exception override circuit

A method and apparatus for implementing FIR filters in a processor includes a plurality of execution units executing instructions of an instruction set. The execution units include a number of FIR filter circuits, each of which is associated with a corresponding one of a number FIR filter instructions. Furthermore, each of the FIR filter circuits is and dedicated exclusively to executing its corresponding one of the FIR filter instructions. Each FIR filter execution unit receives input data and provides filtered output data.

System and method for implementing finite impulse response filter in an audio processor

A non-contacting inductive interconnect of a three-dimensional integrated circuit includes a first silicon substrate having a first inductive loop. A first layer of high permeability material is deposited on the first silicon substrate that has the first inductive loop forming a first high permeability structure. The circuit further includes a second silicon substrate having a second inductive loop. A magnetic coupling is formed between the first inductive loop and the second inductive loop. The first high permeability structure can enhance the magnetic coupling between the first inductive loop and the second inductive loop. In some embodiments, a second layer of the high permeability material is deposited on the second silicon substrate that has the second inductive loop forming a second high permeability structure. The first high permeability structure and the second high permeability structure can form a magnetic circuit coupling the first inductive loop and the second inductive loop.

Non-contacting inductive interconnects

Subject matter disclosed herein relates to arrangements and techniques that provide for sending messages among processing nodes over a network-on-chip (NoC). More particularly, the present disclosure provides an Application Specific Integrated Circuit (ASIC) that includes processing cores and co-processors. The processing cores and co-processors are coupled together with a NoC. Each processing core and co-processor includes two corresponding buffers. A first buffer is for sending messages and a second buffer is for receiving messages. If a processing core or co-processor needs to send a message and the corresponding first buffer is full, if the message includes a flag that indicates a WAIT function, then the processing core and/or co-processor enters a low power state until the first buffer is available; otherwise the message is ignored and not sent. Additionally, if a second buffer is empty, then the corresponding processing core and/or co-processor enters the low power state.

Achieving power saving by a circuit including pluralities of processing cores based on status of the buffers used by the processing cores

Subject matter disclosed herein relates to arrangements and techniques for sending messages directly among processing cores and directly among co-processors over a network-on-chip (NoC). More particularly, the present disclosure provides an Application Specific Integrated Circuit (ASIC) that includes processing cores coupled together with a NoC. Each processing core and co-processor includes two corresponding buffers. A first buffer is for sending messages and a second buffer is for receiving messages. Messages are sent from a processing core directly to another processing core through the NoC. Messages are also sent from a co-processor directly to another co-processor through the NoC.

Sending messages in a network-on-chip and providing a low power state for processing cores

Growing community of inventors

Redmond, WA, United States of America

Richard Thomas Witek