Digital Equipment Corporation

Advanced Micro Devices Corporation

Compaq Computer Corporation, Inc.

Richard T Witek

Richard Lee Sites

David N Cutler

David A Orbits

Wayne M Cardoza

Dileep P Bhandarkar

David Martin Fenwick

Douglas D Williams

Rebecca L Stamm

Stephen Charles Kromer

Douglas J Burns

Timothy J Stanley

Kathryn Jean Hoover

James Joseph Montanaro

Richard Heye

Maurice B Steinman

David Gerard Conroy

R Stephen Polzin

Andrew Halstead Mason

George M Uhler

Scott G Robinson

Judith Shelhorse Hall

Paul T Robinson

Suzanne Plummer

In one embodiment, a system comprises a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, a second interface coupled to the processor unit, and a graphics processing unit. The processor unit comprises at least one processor core and a display controller configured to couple to a display. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.

Integrating display controller into low power processor

An integrated circuit () includes a firewall input terminal, a first circuit (), and a second circuit (). The firewall input terminal is for receiving a firewall input signal. The first circuit () is coupled to a first power supply voltage terminal () and has an output for providing a control signal. The second circuit is coupled to a second power supply voltage terminal (), to the firewall input terminal (), and to the first circuit (). When the firewall input signal is inactive, an activation of the control signal affects the operation of the second circuit. When the firewall input signal is active, an activation of the control signal does not affect the operation of the second circuit.

Integrated circuit with a hibernate mode and method therefor

A data processing system () comprises a system bus (), a plurality of devices () coupled to the system bus (), a bus monitor circuit (), and a clock generator (). The plurality of devices () includes at least one bus master () which is capable of performing accesses on the system bus (). The bus monitor circuit () is coupled to the at least one bus master (), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (). The clock generator () has an output coupled to at least one of the plurality of devices () and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.

Method and apparatus for lowering bus clock frequency in a complex integrated data processing system

A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard. sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed.

Branch performance in high speed processor

A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches to be predicted as taken. Another embodiment uses unused bits in the standard-sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry. An additional feature is the addition of a prefetch instruction which serves to move a block of data to a faster-access cache in the memory hierarchy before the data block is to be used.

Branch prediction in high-performance processor

Apparatus for supporting virtual address aliasing is disclosed in which addresses to a virtual cache are first intercepted. It is determined whether the these addresses are aliased, i.e., more than one virtual address exists for the same location in memory. If not aliased, the addresses are simply passed to the virtual cache. In the case where there is aliasing, however, dealiasing is performed. New addresses are generated and passed to the virtual cache so that the aliased addresses are directed to the same locations in the virtual cache. In this way, an operating system can be supported that uses virtual address aliasing since the CPU can transparently issue aliased virtual addresses. These addresses, however, are directed to the same locations in the virtual cache so that the addresses are not aliased from the perspective of the cache, thus avoiding the need for other hardware to compensate for the aliasing. The modification, however, does not substantially impact latency. The invention is most useful in situations in which the operating system merely requires the potential for aliasing between active processes.

Limited virtual address aliasing and fast context switching with

A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Byte-compare operation for high-performance processor

An apparatus for generating control signals of a microprocessor includes a memory, for example, a pattern holding register storing an arbitrary bit pattern. The holding register can be loaded by software. A shift register is connected to receive the bit pattern from the pattern register. An output pin of the microprocessor receives each bit of the arbitrary bit pattern, directly, or indirectly via a bus interface unit, at a rate determined by a clock signal to generate control signals for arbitrary external devices.

Apparatus and method for generating external interface signals in a

A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream. Performance can be speeded up by predicting the target of a branch and prefetching the new instruction based upon this prediction; a branch prediction rule is followed that requires all forward branches to be predicted not-taken and all backward branches (as is common for loops) to be predicted as taken. Another performance improvement makes use of unused bits in the standard-sized instruction to provide a hint of the expected target address for jump and jump to subroutine instructions or the like. The target can thus be prefetched before the actual address has been calculated and placed in a register. In addition, the unused displacement part of the jump instruction can contain a field to define the actual type of jump, i.e., jump, jump to subroutine, return from subroutine, and thus place a predicted target address in a stack to allow prefetching before the instruction has been executed. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry. An additional feature is the addition of a prefetch instruction which serves to move a block of data to a faster-access cache in the memory hierarchy before the data block is to be used.

Prefetch instruction for improving performance in reduced instruction

A system or method is provided for translating a first program code to a second program code and for executing the second program code while preserving instruction state-atomicity of the first code. The first program code is executable on a computer having a first architecture adapted to a first instruction set and the second program code is executable on a computer having a memory and register state and a second architecture adapted to a second instruction set that is reduced relative to the first instruction set. A first computer translates the first code instructions to corresponding second code instructions in accordance with a pattern code that defines first code instructions in terms of second code instructions. The second code instructions for each first code instruction organized in a granular instruction sequence having in order at least two groups, a first group having a first subgroup including second code read instructions and a second subgroup including modify instructions and a second group having a third subgroup including state update instructions subject to exception, including any special write instruction required to implement the first code instruction being translated, and a fourth subgroup including state update instructions free of exception.

System and method for preserving instruction state-atomicity for

Method and apparatus for eliminating branches using conditional move

A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry.

Virtual to physical address translation scheme with granularity hint for

A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

Pipeline utilizing an integral cache for transferring data to and from a

A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

Growing community of inventors

Littleton, MA, United States of America

Richard T Witek