Information Storage Devices, Inc.

Sandisk Corporation

Linear Technology Corporation

General Lasertronics Corporation

Richard T Simko

Trevor A Blyth

Daniel C Guterman

Kevin M Conley

Geoffrey Steven Gongwer

Shahzad Khalid

Hieu Van Tran

Sakhawat M Khan

A laser-based coating removal method debonds a film from a substrate rather than ablating the film. A laser light is transmitted through a transparent film to an underlying bonding layer for bonding the film to one or more additional films and/or a substrate. The laser light is absorbed at the bonding layer and the transparent film is released. In some embodiments, after the transparent film is released it is able to be physically removed.

Laser film debonding method

The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.

Writable tracking cells

A non-volatile memory element is operated, in part, in two phases. During the first phase, a voltage is applied to a first node coupled to the nonvolatile memory element to generate an initial voltage. During the second phase, a voltage is coupled through at least one capacitor to charge pump the initial voltage to a level sufficient for programming or erasing the non-volatile memory element.

Floating gate nonvolatile memory circuits and methods

Methods and apparatus for achieving analog storage in a non-volatile memory array. The array consists of memory cells that utilize Fowler-Nordheim tunneling for erasure and hot electron injection for programming. Writing into a cell is performed by an initial erasure followed by a controlled sequence of program operations during which the cell is programmed in small increments. The stored voltage is read after each program step and when the voltage read back from the cell is equal or just beyond the desired analog level, the sequence of program steps is terminated. The read condition for the cell applies a positive voltage to the drain or common line and a positive voltage to the control gate. The source is connected through a load device to a negative (ground) supply. The output from the cell is the actual voltage that exists at the source node. There is no current sensing or comparison with a reference voltage to determine the output state. A digital number can be represented by assigning a specific analog level to a digital number. The range of digital numbers that can be represented is determined by the analog voltage range divided by the accuracy to which the voltage may be stored and reliably retrieved. Other aspects and features of the invention are disclosed.

Non-volatile electrically alterable semiconductor memory for analog and

The present invention discloses methods and apparatus for implementing a clocked high voltage switch involving MOS devices. The switching is from a high voltage source typically at 21V to ground. An intermediate voltage source typically at 11V is introduced for reducing the gated breakdown voltage requirement to approximately 10V. This reduced gated breakdown voltage requirement is easily met by special layout methods applied to various transistors in the circuit. The basic layout methods include the terminating of the field implant region near the N+P junction to expose the N+ diffusion over the P substrate to increase the junction breakdown and the gated diode breakdown, and the use of short channel length to reduce the threshold voltage.

Clocked high voltage switch

The present invention discloses methods and apparatus for implementing a single-transistor cell EEPROM array for analog or digital storage. The single-transistor storage cell is made possible by continuously maintaining a net negative charge on the floating gate of the EEPROM storage transistor. Furthermore, according to the present invention, a dense layout of the single-transistor cells is possible by sharing a common diffusion region between the transistors located in the same row and the transistors located in one adjacent row. This common diffusion region functions as a source in the erase and program modes, and as a drain in the read mode. Moreover, the common diffusion feature of the present invention allows the use of a single level of metal in distributing the various operating voltages to the EEPROM storage transistors. Further, utilizing a single level of metal allows for a simple and dense fabrication and also reduces the parasitic capacitances in the EEPROM storage array. Array operating voltages are chosen such that 'program disturbance' is eliminated on cells adjacent to a cell undergoing programming. Finally, the present invention utilizes only a single polarity of operating voltages.

Single-transistor cell EEPROM array for analog or digital storage

Integrated circuit system for analog signal recording and playback having improved performance and a very high level of integration. The integrated circuit is complete with preamplifier, automatic gain control, filter, fixed references including a band gap reference, trimming, power output amplifier, memory array, multiple closed loop sample and hold circuits, column decoder, column driver, row decoder, address counters, master oscillator and chip function timing circuits including sample clock, charge pumps, high voltage regulator and waveshapers, low VCC detector, power-on reset and recording reference circuits on a single chip. The system uses a writable analog reference scheme to put many error sources in the common mode, and provides a double ended output for maximum power output in a limited voltage range, and to allow direct connection to a speaker. Trim bits are provided for trimming the oscillator and filter so that the filter characteristics match and track the oscillator frequency and provision is made for absolute addressing and digital end of message markers. Programming is by way of a multi level iterative write process for high resolution.

Integrated circuit system for analog signal recording and playback

Source follower storage cell and improved method and apparatus for iterative write for integrated circuit analog recording and playback which provides increased resolution in the stored signal and increased accuracy and stability of the storage and readout capabilities of the device. The storage cell is configured wherein the electrically alterable MOS storage device is connected in a source follower configuration, which provides a one to one relationship between the variation in the floating gate storage charge and the variation in the output voltage, and for high load resistance, relative insensitivity to load characteristics. The write process and circuitry provides a multi iterative programming technique wherein a series of coarse pulses program a cell to the approximate desired value, with a series of fine pulses referenced to the last coarse pulse being used for programming the respective cell in fine increments to a desired final programming level. Still finer levels of programming can be used.

Source follower storage cell and improved method and apparatus for

A writable distributed non-volatile analog reference system and method for analog signal recording and playback having application in integrated circuits which sample and directly store analog information. The invention is useful to facilitate the sensing of analog levels stored in nonvolatile memory cells where the analog levels are played back such as to reproduce voice or music or tone information. In accordance with the method, one or more reference storage columns are included in the array at each side of the storage cell array and are used to store a reference signal at the same time that the adjacent storage cell stores a signal sample. On playback, the stored reference signals for the row of the array are read back and weighted relative to each other in accordance with the relative row position of the signal storage cell being simultaneously read, with the output signal being taken as the difference between the signal sample read back and the reference signals read back (as weighted relative to each other as per the position in the row of the signal cell). This differencing places many error sources in the common mode, thereby substantially eliminating the same from the output signal. A specific memory array organization and the operation thereof is disclosed.

Writable distributed non-volatile analog reference system and method for

The present invention is a high density integrated circuit analog signal recording and playback system. The recording and playback system is based upon an array storing analog signals. The array has rows and columns of non-volatile memory cells to store the signal information. Analog column read/write circuitry is used to both store the analog information and retrieve it on a real time basis, using interleaving of analog information on a plurality of sample/hold circuits prior to storage in the array to increase throughput.

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Los Altos Hills, CA, United States of America

Richard T Simko