Xicor Corporation

Intel Corporation

Richard T Simko

William H Owen, Iii

Wallace E Tchon

Phillip J Salsbury

Joseph Drori

Low power consumption methods and apparatus for distributing and controlling on-chip generated high voltage, for programming nonvolatile memory arrays and the like.

Integrated high voltage distribution and control systems

Integrated high voltage clamping methods and devices which provide a controllable 'soft' clamping action. The systems are particularly useful for 'on-chip' EEPROM high voltage power supplies.

Integrated circuit high voltage clamping systems

Integrated circuit high voltage ramp rate control methods and devices which provide a controllable ramp rate action. The systems are particularly useful for 'on-chip' EEPROM high voltage power supplies.

High voltage ramp rate control systems

A compact, floating gate, nonvolatile, electrically-alterable memory device fabricated with three layers of polysilicon and a substrate coupling electrode is described. A particular form of the device utilizes asperities to promote tunnel current flow through relatively thick oxides by means of relatively low average applied voltages. The use of four electrode layers leads to an extremely dense cell and memory array configuration. The substrate electrode is used to establish bias voltages in the cell.

Dense nonvolatile electrically-alterable memory device with substrate

An integrated circuit system for generating a regulated high voltage tunneling pulse whose voltage level varies as a function of the voltage level needed to initiate tunneling of electrons across one or more dielectric gaps between respective first and second regions. The voltage level of initial electron tunneling is compared with a predetermined voltage margin so as to cause said generated tunneling voltage pulse to have a voltage level equal to the sum of said detected tunneling voltage and said voltage margin. The tunneling voltage pulse is then maintained substantially at this level for a predetermined duration before the tunneling pulse is discharged.

Integrated circuit high voltage pulse generator system

Nonvolatile, integrated metal-oxide semiconductor random access memory systems utilizing integrated floating gate circuit elements, and integrated means for the generation and control of high voltages in the provision of self-contained, nonvolatile electrically-alterable static RAM circuit systems.

Nonvolatile static random access memory system

Integrated circuit system for generating a rise-time regulated and level controlled high voltage pulse utilizing a plurality of diode-connected stages driven by capacitively coupled low voltage clocks. The maximum output voltage may be controlled by a gated diode reference device, which provides a reference voltage independent of power supply voltage. A feedback circuit may be provided which controls the high voltage rise time by modulating the effective low voltage clock amplitude driving the high voltage generator. A MOS logic level interface circuit may also be provided for sensing achievement of the predetermined high voltage level.

Integrated rise-time regulated voltage generator systems

A compact, floating gate, nonvolatile, electrically-alterable memory device fabricated with four layers of polysilicon is described. A particular form of the device utilizes asperities to promote tunnel current flow through relatively thick oxides by means of relatively low average applied voltages. The use of four electrode layers leads to an extremely dense cell and memory array configuration.

Dense nonvolatile electrically-alterable memory devices with four layer

Nonvolatile, semiconductor random access memory cells comprising a static, RAM cell and a nonvolatile memory element which may be interconnected with the static random-access memory cell by capacitative coupling, such that the RAM cell contents may be directly copied to the nonvolatile element, and such that the nonvolatile memory cell contents will be copied to the RAM cell upon applying power to the RAM cell. The nonvolatile memory element may be a substrate-coupled floating gate cell incorporating self-regulated and asperity enhanced tunnel currents.

Nonvolatile static random access memory devices

Nonvolatile semiconductor electrically-alterable, floating-gate memory methods and devices which utilize substrate coupling for self-regulated, tunnel-current-shaping to provide improved device characteristics. The substrate coupling also facilitates the cell interconnection to other circuit elements.

Substrate coupled floating gate memory cell

An MOS memory cell which includes a floating gate charged from the substrate by avalanche injection. Charge is removed from the floating gate to an erasing gate by tunneling. Sharp edges on the polycrystalline silicon floating gate provide an enhanced electric field to overcome the silicon/silicon oxide barrier, thus permitting charge to be transferred from the floating gate to the erasing gate.

Electrically programmable and electrically erasable MOS memory cell

A triple layer polysilicon cell for use in an electrically erasable PROM or for a discretionary circuit connector is described. Tunneling is employed to transfer charge to a floating gate from a programming gate and also to transfer charge from the floating gate to an erasing gate. Through light doping steps, the first layer of polysilicon (programming gate) and a second layer of polysilicon (floating gate) include rough surfaces. These rough surfaces provide enhanced electric fields which allow tunneling through relatively thick oxides.

Triple layer polysilicon cell

A method for forming a narrow gap in a material in which a first masking layer and a second masking layer are disposed on a layer of material and are selectively removed to expose a portion of the surface of the material. A third masking layer is then disposed on the material. The first and third layers and the material are then selectively etched to form such narrow gap. The portions of the material separated by the gap may be used as MOS integrated circuit gates and a gate may also be formed in the gap by first depositing an insulating layer in the gap and then filling the gap with a conductive material.

Growing community of inventors

Los Altos, CA, United States of America

Richard T Simko