Silicon Laboratories Inc.

Silicon Clocks, Inc.

Silicon Labs Sc, Inc.

Other

Richard Steven Miller

Andrew D McCraith

Emmanuel Philippe Quevy

Manu Seth

Mir Bahram Ghaderi

David L Brubaker

Jagdeep Singh Bal

Colin Wai Mun Leong

Ion E Opris

Gabriel-Gheorghe Dumitrescu

Kristy M Miller

A hybrid system having a non-MEMS device and a MEMS device is described. The apparatus includes a non-MEMS device and an integrated circuit including a MEMS device, the integrated circuit formed on a substrate. The integrated circuit includes a control circuit for the non-MEMS device and a MEMS control circuit for the MEMS device.

Hybrid system having a non-MEMS device and a MEMS device

A frequency-control circuit, which is configured to receive a first signal having a first untuned frequency from a first oscillator, and to alter one or more pulses of the first signal to tune an output frequency of an output clock signal to have an average frequency at the desired target frequency. In some embodiments, the frequency-control circuit receives a signal from a single oscillator to generate a calibrated, precise, and temperature-stable clock.

Precision, temperature stable clock using a frequency-control circuit and a single oscillator

A frequency-control circuit, which is configured to receive a first signal having a first untuned frequency from a first oscillator, and to alter one or more pulses of the first signal to tune an output frequency of an output clock signal to have an average frequency at the desired target frequency. In some embodiments, the two oscillators of intentionally different frequencies are periodically switched at a duty factor, which is dependent on an absolute temperature, to generate a calibrated, precise, and temperature-stable clock.

Precision, temperature stable clock using a frequency-control circuit and dual oscillators

A circuit for generating an output oscillation signal with low jitter includes an oscillator to generate an oscillation signal at an initial frequency based upon a control input to vary an amplitude of the oscillation signal. A first frequency multiplier multiplies the oscillation signal to result in a first signal with first frequency and first undesired frequency components. A filter minimizes the first undesired frequency components of the first signal. A second frequency multiplier multiplies the first signal to result in the output oscillation signal with second frequency and second undesired frequency components. A second feedback circuit compares a predetermined range and at least one of the first signal and the output oscillation signal to result in a reference value. A first feedback circuit varies the control input based upon a comparison between the reference value and the amplitude of the oscillation signal to minimize the second undesired frequency components.

Systems and methods for generating an output oscillation signal with low jitter

A hybrid frequency synthesizer includes an analog phase lock loop (PLL), a digital PLL, and a control circuit to control an output oscillator. The control circuit assigns control of the output oscillator between the analog PLL and/or the digital PLL depending on a state of lock of the analog PLL and/or the digital PLL. During a frequency acquisition mode, the digital PLL provides a coarse control of the output oscillator. During a phase capture mode, the analog PLL provides a fine control and the digital PLL provides a coarse control of the output oscillator. During the phase capture mode, the analog PLL control signal and the digital PLL control signal may be given a percentage of control over the output oscillator depending on the state of lock of the analog PLL and/or the digital PLL. During a phase lock mode, the analog PLL controls the output oscillator.

Method and apparatus for a hybrid phase lock loop frequency synthesizer

A hybrid frequency synthesizer includes an analog phase lock loop (PLL), a PLL, and a control circuit to control an output oscillator. The control circuit combines a control signal from the analog PLL with a control signal from the digital PLL to form a composite control signal. The composite control signal is conditioned depending on a state of lock of the analog PLL and/or the digital PLL. The composite signal controls the phase and frequency of the output oscillator. The analog control signal and the digital PLL control signal may be given a percentage of over the hybrid frequency synthesizer depending on the state of lock of the PLL and/or the digital PLL. The composite control signal provides both rapid, accurate, and robust acquisition by the digital PLL, and a smooth transition thereafter to low noise phase lock by the analog PLL.

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Los Altos, CA, United States of America

Richard Steven Miller