Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Gm Global Technolgoy Operations, Inc.

Richard Soja

William C Moyer

Ray Charles Marshall

Timothy J Strauss

Nancy H Amedeo

James B Eifert

Michael R Grimes

James A Stephens

George Adrian Ciusleanu

Antonio Mauricio Brochi

Andrey Kovalev

Sergej Makevev

Marianna Soboleva

Andrey Artamonov

Mike Pauwels

Chad Peckham

In a data processing system having a processor and a memory protection unit (MPU), a method includes scheduling, in the processor, a new process to be executed; writing a process identifier (PID) corresponding to the new process into storage circuitry of the MPU; in response to updating the storage circuitry with the PID, configuring the MPU with region descriptors corresponding to the new process; configuring, by an operating system of the processor, the processor to execute the new process in parallel with the configuring the MPU with the region descriptors; and when the configuring the MPU is complete, giving control to the new process to execute on the processor.

Data processing unit having a memory protection unit

A technique that reduces the startup time of a processing system authenticates a proxy for an image stored in tracked memory instead of authenticating the image stored in the tracked memory. A controller generates an alteration log authentication code based on an alteration log that is updated prior to programming the image stored in tracked memory. The controller records an alteration log authentication code in secure memory. The alteration log is indirectly related to a most recent image stored in the tracked memory. Authentication of the image of the alteration log is used as a proxy for authentication of the image stored in tracked memory, which is performed only when the tracked memory is modified. Use of the contents of the alteration log as a proxy for the contents of tracked memory accelerates the startup time of the system.

Fast secure boot from embedded flash memory

A technique for providing access to a first storage structure of a system includes exposing a first key of a plurality of first keys stored in a second storage structure in response to a select code based on a plurality of corresponding select records stored in one-time programmable storage elements of the second memory structure. The technique includes providing the first key as a current first key of a memory access controller. Only one of the plurality of first keys stored in the second storage structure may be exposed at a time and other first keys of the plurality of first keys stored in the second storage structure are inaccessible from the second storage structure at the time.

Key storage and revocation in a secure memory system

A hardware security module (HSM) transitions a first signal from a first state to a second state and transitions a second signal from a first state to a second state when a request to change boot code is received. In response to receipt of a boot request, the HSM, when the first signal is in the first state and the second signal is in the first state: does not execute the hash function; and maintains the second signal in the first state. An actuator control module, in response to the receipt of the boot request: executes the boot code when the second signal is in the first state; and does not execute the boot code when the second signal is in the second state.

Boot control systems and methods for vehicles

A reconfigurable register device includes an arrangement of storage elements arranged sequentially in a chain structure. Each storage element stores a state of a binary signal. A combinatorial logic circuitry connectable to the arrangement of storage elements enables the arrangement of storage elements to form a binary synchronous counter. A bypass logic circuitry connectable to the arrangement of storage elements enables the arrangement of storage elements to form a serial shift register. A switching circuitry has a mode signal input terminal receiving a mode signal indicative of at least one of a counter mode and a shift register mode. The switching circuitry is configured to connect the arrangement of storage elements to the combinatory logic circuitry if the mode signal indicates the counter mode, and to connect the arrangement of storage elements to the bypass logic circuitry if the mode signal indicates the shift register mode.

Configurable serial and pulse width modulation interface

A semiconductor device includes, in various embodiments, a memory and a processor, with the processor configured to perform a permission check prior to execution of a memory-access instruction. The permission check comprises evaluating a permission attribute of the memory-access instruction and a permission attribute of a memory location to be accessed. The memory-access instruction is denied unless the permission attribute of the memory-access instruction is compatible with the permission attribute of the memory location to be accessed. In various embodiments, permission attributes are obtained by the processor from a one-time-programmable (OTP) memory module. In various embodiments, the permission attributes are determined based on a source address of the memory-access instruction and an address of the memory location to be accessed. In various embodiments, the OTP memory module stores permission settings that are based on the identity of suppliers for various portions of code stored in the memory.

Trusted execution and access protection for embedded memory

A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied.

Non-volatile storage alteration tracking

A method includes providing an effective address, providing an address space identifier which identifies a currently executing process, providing a mapping modifier to form a modified address space identifier where the mapping modifier is based on at least one external signal generated outside the processor, using the effective address and the modified address space identifier to form a logical address, and providing a physical address corresponding to the logical address. When the effective address has a first effective address value, the address space identifier has a first address space identifier value, and the mapping modifier has a first mapping value, the physical address has a first physical address value. When the effective address has the first effective address value, the address space identifier has the first address space identifier value, and the mapping modifier has a second mapping value, the physical address has a second physical address value.

Non-intrusive address mapping having a modified address space identifier and circuitry therefor

In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.

Processor and method for altering address translation

In a method for determining a worst case service latency, first a number of accesses granted to requesting channels during the worst case service latency is determined. Therefore, the ordered list of priorities and the priority passing rules of a scheduler of the queuing system is taken into consideration so that an accurate number of access requests during the worst case service latency results. According to the number of access requests, states are selected for the different requesting channels so that the sum of the state execution times reaches a maximum according to the applicable priority passing rules. This method can be implemented by a computer program and can be advantageously used for design of an apparatus which incorporates a queuing system, such as in automobile electronics.

Method for determining the number of accesses granted during WCL and apparatus

A test system (10) for testing real-time angle/time based control systems includes a digital signal generator (16), a multi-channel pulse analyzer (22), and a test system host (12). The test system host (12) controls the execution of a user generated test script. The script specifies test stimuli, external angle/time event interrupts for use by the digital signal generator (16) to a device under test (DUT) (20), and angle/time triggers used by the analyzer (22) to test the DUT (20). Using the test stimuli and external angle/time event interrupts, the DUT (20) is exercised to determine whether or not the DUT (20) and corresponding control system software operate properly. Output data from the DUT (20) are monitored by the pulse analyzer (22), which records the output data based on information specified in the script. Test results are then retrieved by the test system host (12).

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Richard Soja