Altera Corporation

Richard Shaw Terrill

Chiakang Sung

Richard G Cliff

Srinivas T Reddy

Kerry S Veenstra

Rina Raman

Andreas Papaliolios

Robert R Bielby

Robert Richard Noel Bielby

Donald F Faria

Scott D Redman

Dennis Mak

A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The prepackaged PLDs and the ability to use the substrate as a burn-in vehicle for the FPIC die results in reliable and reworkable assembly process with minimized yield loss.

Method of making a high density programmable logic device in a multichip module package

Apparatus and methods for configuring a plurality of programmable logic devices which include the steps of providing a source of configuration data and transferring the configuration data directly from the source to each of the programmable logic devices. In some embodiments, the methods permit the programmable logic devices to configure themselves without the intervention of an intelligent host such as a CPU, a microcontroller, or other types of intelligent logic. In other embodiments, configuration data files are used in conjunction with an intelligent host to configure the programmable logic devices. Configuration is performed at power-up or, alternatively, under user or software control.

Programming circuits and techniques for programmable logic

Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgment from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

Techniques for programming programmable logic array devices

A computerized system restricts full revelation of certain information to a user, while also performing limited processing of the information for the user for evaluation. The information is encrypted and therefore may be widely distributed without fear of revelation. An authorization code from the user specifies the type(s) of processing that are permitted, wherein different types of processing produce different type(s) of output that reveal to different degrees the information. The type(s) of output include output which represent more than mere reproduction of the information. A particularly appropriate implementation of the present invention is in the area of Electronic Design Automation (EDA) for logic design.

Access restriction to circuit designs

A high performance single package multi-chip module multiplies the logic density of the highest density monolithic programmable logic device (PLD). A dual-sided substrate carries multiple prepackaged PLDs on a top side and a field programmable interconnect (FPIC) die on a bottom side. The input/output terminals of the PLDs are interconnected with the FPIC die in a scrambled fashion to reduce signal skew.

High-density programmable logic device in a multi-chip module package

Programming circuits and techniques for programming logic

Programmable logic array devices are programmed from programming devices in networks that facilitate programming any number of such logic devices with programs of any size or complexity. The source of programming data and control may be a microprocessor or one or more serial EPROMs, one EPROM being equipped with a clock circuit. Several parallel data streams may be used to speed up the programming operation. A clock circuit with a programmably variable speed may be provided to facilitate programming logic devices with different speed characteristics. The programming protocol may include an acknowledgement from the logic device(s) to the programming data source after each programming data transmission so that the source can automatically transmit programming data at the speed at which the logic device is able to accept that data.

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Sunnyvale, CA, United States of America

Richard Shaw Terrill