Avago Technologies General IP (singapore) Pte. Ltd.

Agilent Technologies, Inc.

Avago Technologies General IP Pte, Ltd.

Avago Technologies Enterprise IP (singapore) Pte. Ltd.

Richard S Rodgers

Howard L Porter

Troy Horst Frerichs

Jeffrey R Rearick

Jason Todd Gentry

Brady A Koenig

Cory D Groth

Scott T Evans

Gerald L Esch, Jr

Benjamin P Haugestuen

A floor planning tool is provided that performs the functions that are typically performed by floor planning tools, but in addition, determines the supply of routing resources and the demand on routing resources for all routing channels while applying variable routing rules and static timing estimations to arrive at a preliminary routed floor plan. This drastically reduces the number of iterations that subsequently will need to be performed by the floor planning tool and by routing and static timing analysis tools to arrive at a final routed floor plan.

Computer system and method for performing a routing supply and demand analysis during the floor planning stage of an integrated circuit design process

Differences between block interfaces of a partitioned logic block in two floorplans of an integrated circuit can be determined by comparing an image of pins of a partitioned logic block in a first floorplan of the integrated circuit with an image of pins of the partitioned logic block in a second floorplan of the integrated circuit. The second floorplan can represent a new floorplan design resulting from a change to an integrated circuit design represented by the first floorplan. If no differences exist between pins of the partitioned logic block in the first and second floorplans, information representing the partitioned logic block in the second floorplan can be substituted with information representing the partitioned logic block in the first floorplan.

System and method for ensuring partitioned block physical compatibility between revisions of an integrated circuit design

A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not be modified. A leakage optimization procedure is responsive to a slow corner timing database and timing constraints for a slow corner. The procedure is configurable and includes the repair of register transition violations. The procedure is performed on a select number of paths before an adjusted timing slack value is determined and cells are addressed in response to the number of failing timing paths associated with a cell. Some embodiments generate information in a router compatible format that identifies a desired modification to the top-level integrated circuit design.

Systems, methods, and programs for leakage power and timing optimization in integrated circuit designs

Systems and methods are disclosed herein for determining the placement of a standard cell, representing a semiconductor component in a design stage, on an integrated circuit die. One embodiment of a method, among others, comprises analyzing regions of a semiconductor die with respect to the susceptibility of the region to be exposed to radiation. This method further comprises placing the standard cell in one of the analyzed regions of the semiconductor die, the standard cell being placed based on the sensitivity of the standard cell to radiation. The method may also comprise running an algorithm, e.g. using a component placement engine, for determining the placement of semiconductor components on an integrated circuit die.

Determining the placement of semiconductor components on an integrated circuit

An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (f) at which IC operation is sought to be determined, measuring the actual clock period (T) at a clock output, scan testing the IC, measuring the actual clock period (T) at the clock output, determining a delay by calculating the difference between Tand T, and compensating for the delay by increasing the clock frequency during scan test.

Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)

Systems and methods are disclosed herein for determining the placement of storage and non-storage cells or components, representing a semiconductor component in a design stage, on an integrated circuit die. In one embodiment, regions of a semiconductor die are analyzed with respect to the susceptibility of a region to be exposed to radiation and the distance between a storage component and a local clock buffer. The radiation, for instance, may be alpha particle radiation emitted from lead (Pb) isotopes in solder bumps formed on the integrated circuit die. The distance, spatial positioning and/or physical proximity of a selected local clock buffer and a storage component are preferably selected so that the skew between the storage component and the local clock buffer is about 30 picoseconds or less. Other maximum skews may be employed, however, such as about 100 picoseconds or less, about 90 picoseconds or less, about 80 picoseconds or less, about 70 picoseconds or less, about 60 picoseconds or less, about 50 picoseconds or less, about 40 picoseconds or less, about 20 picoseconds or less, about 10 picoseconds or less and about 5 picoseconds or less.

Alpha-particle-tolerant semiconductor die systems, devices, components and methods for optimizing clock rates and minimizing die size

An apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC) includes operating a clock associated with the IC at a frequency (fTARGET) at which IC operation is sought to be determined, measuring the actual clock period (TCLOCK_OUT) at a clock output, scan testing the IC, measuring the actual clock period (TSCAN_CLOCK_OUT) at the clock output, determining a delay by calculating the difference between TSCAN_CLOCK_OUT and TOLOCK_OUT, and compensating for the delay by increasing the clock frequency during scan test.

A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which are positioned so that no two ports of that block lie within the same routing track parallel to the closest portion of a primary bus route. All other blocks, termed secondary blocks, have ports that are positioned so that no two ports of any secondary block reside within the same routing track perpendicular to the closest portion of the primary bus route. A primary connection for each signal of the signal bus is then placed over each port of the primary block substantially along the length of the primary route. Each port of each secondary block then has a secondary track connecting it in a perpendicular fashion to the proper primary track.

Integrated circuit routing resource optimization algorithm for random port ordering

A method for minimizing clock skew in a balanced tree when interfacing to an unbalanced load is presented. Unused portions of the balanced tree are replaced by a loading equivalent circuit to create a physically balanced load. In the preferred embodiment, the loading equivalent circuit is implemented with a single-pole resistor-capacitor circuit that has been modeled to match the RC characteristics of the replaced branch of the tree.

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Fort Collins, CO, United States of America

Richard S Rodgers