3com Corporation

U.S. Ethernet Innovations, LLC

3 Com Corporation

Richard S Reid

Glenn William Connery

Paul William Sherer

Niles E Strohl

James P Rivers

Richard J Hausman

Cynthia Zikmund

Chi-Lie Wang

Anthony Liem Pan

William Paul Sherer

Eric Roger Davis

Gary Michael Jaszewski

Marwan A Fawal

David R Brown

Brian A Petersen

In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

Programmed I/O ethernet adapter with early interrupts for accelerating data transfer

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

An adapter is provided with intelligence that allows it to separate the header parts of a packet being received from the payload it carries, and in most cases move the payload directly into a destination buffer at the application layer or file system layer. Copies by the intermediate layers of the protocol stack are bypassed, reducing the number of times that the payload of a communication must be copied by the host system. At the network interface, a plurality of packets is received, and the payload of each is bypassed directly into the target destination buffer. The network interface device identifies the packets which are in the sequence of packets carrying payload to be stored in the target buffer by the flow specification carried with such packets. Also, the packets carrying data payload for the file include a sequence number or other identifier by which the network interface is able to determine the offset within the target buffer to which the packet is to be stored.

Receive processing with network protocol bypass

The present invention provides a device which facilitates communications between a computer system and a data network by buffering data in transit between the computer system and the data network in a single buffer memory which can be flexibly partitioned into separate transmit and receive buffers. This flexible partitioning allows the relative sizes of the transmit and receive buffers to be optimized across a wide range of buses, data networks and network usage patterns. The transmit and receive buffers are structured as ring buffers within respectively allocated portions of the buffer memory. The buffer memory is controlled by a simple finite state machine controller, which is free from the performance impediments and higher cost associated with a microprocessor-based controller. The present invention also provides support for retransmission of packets that encounter transmission problems such as collisions during transmissions on the data network. The present invention additionally provides the ability to discard incomplete packets.

System to optimize packet buffer utilization via selectively partitioned transmit and receive buffer portions

A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates interrupts after a delay determined by an interrupt deferral mechanism, which includes one or more timers and/or one or more counters. Interrupts are generated, for example, after a predetermined time has elapsed after a DMA completion or after a certain number of packets are counted.

Network and adaptor with time-based and packet number based interrupt

Programmed I/O ethernet adapter with early interrupt and DMA control for

One embodiment of the invention includes a transformer that is at least partially formed on a substrate. The transformer is for electrical isolation and signal filtering. The transformer includes the following elements. A portion of the substrate has two holes through the substrate. A ferrite core is formed in a loop through the two holes. A primary winding is made of a first metal trace. The first metal trace is formed in a spiral around one hole. The first metal trace has at least two primary terminals acting as an input to the transformer. The transformer also includes a secondary winding. The secondary winding is made of a second metal trace. The second metal trace is formed in a spiral around the other hole. The second metal trace has at least two secondary terminals acting as an output from the transformer. The parasitic capacitance of the first metal trace and the magnetizing inductance of the primary winding cause signals received at the primary terminals to be filtered as the signals are passed through the transformer to the secondary terminals.

Isolation and signal filter transformer

A network transmitter schedules packets so that packets are transmitted to a host or group of hosts so as not to overload any particular part of the network. In an embodiment, the transmitter uses packet data structures with a schedule indication for packets placed in the queue so that an independently running adaptor may know when to remove packets from the queue and transmit them. In an alternative embodiment, packets are scheduled by setting a future interrupt for transmitting a packet or group of packets. In a further embodiment, packets are placed in temporal sets where a temporal set is a group of packets that can be transmitted in succession without violating the bandwidth limitations of any network segment.

Method and apparatus for time-based download control

In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter may also be programmed to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.

Programmed I/O ethernet adapter with early interrupts for accelerating

Apparatus for simulating a stack structure using a single register and a

In a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts a start key via a sequence of write commands via the bus to any adapters on the bus and to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves causing the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e.g., an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter.

Method and apparatus for configuring a selected adapter unit on a common

A computer bus adapter device which is coupled to a true parallel computer bus is automatically set to a pre-determined configuration in response to configuration data provided to the bus by a host process. During a set-up portion of an initialization procedure, the adapter device recognizes a data sequence and uses information based on the recognized data sequence to configure itself to respond to its host process. In a specific embodiment, the desired configuration information is stored in non-volatile storage associated with the host process, such as a magnetic file or a non-volatile random access memory.

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Mountain View, CA, United States of America

Richard S Reid