Motorola Corporation

Richard S Raimi

James S Golab

Carl P Pixley

Javier Prado

A simulation monitor (502) automatically generates a monitor file (510) from a static timer output file (504). The monitor file instantiates a function, a firing equation, that triggers if and only if a critical timing path also triggers. The monitor file is written in a high level language description, suitable for efficient simulation. The test vectors which trigger the firing equation can thereby be monitored and used for hardware test at a later time. The invention may be extended to monitor other conditions of interest.

Method of monitoring a computer simulation of an electrical circuit

Measurement of the test coverage of digital simulation of electronic circuitry is obtained (54). A Composite Circuit Model (60) has two parts: a Target Circuit Model (64) and an Environment Circuit Model (62). The Environment Circuit Model (62) models the behavior of inputs to the Target Circuit (64). The Composite Circuit Model (60) is translated into implicit FSM representations utilizing BDDs. A State Bin Transition Relation is formed which represents allowable transitions among user-specified sets of states or State Bins, and a representation of the reachable State Bins is built (94). A comparison is made (102) between data accumulated over one or more simulations (40) of the Target Circuit (64) and the data contained in the State Bin Transition Relation and the representation of the reachable State Bins. Output (52) is then generated showing which sets of circuit states were and weren't visited and which transitions allowed by the State Bin Transition Relation were and weren't taken during the simulations.

Measurement of digital circuit simulation test coverage utilizing BDDs

A method and apparatus, for determining test coverage estimation for an electrical circuit (10) formed in accordance with an original high level description (21), uses a central processing unit (CPU 18). The CPU (18) accesses the description (21) and parses the high level language description (21) to allow for the generation of new code. This new code is intermixed with code from the description (21) to form a new high level description (22) which not only can be used to simulate the electrical circuit but can collect test coverage information. A simulation of the description (22) is performed using test vector inputs to simulate operation of the circuit (10) and estimate it's test coverage for the test vectors. Various warning/error messages are derived to indicate where the test vectors are lacking in test coverage.

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Austin, TX, United States of America

Richard S Raimi