Northern Telecom Limited

Mosaid, Inc.

Richard S Phillips

In a self-latching sense amplifier, a first pair of matched transistors is connected as a differential pair. A second pair of matched transistors is connected each to a respective one of the transistors of the first pair as a load transistor. A feedback circuit responsive to a differential output of the differential pair cross-couples the load transistors when the differential output is greater than a threshold value, and defeats cross-coupling of the load transistors when the differential output is less than the threshold value. The cross-coupling causes the output of the sense amplifier to latch. The sense amplifier is useful in memory circuits in which it is desired to shut down core components between memory operations to conserve power, and in other small signal detection circuits.

Sense amplifier and method for its operation

A reference voltage generator can provide RAMs (random access memories) with a reference voltage (generally mid-way between a supply voltage and a common potential), with improved follower characteristics. When the supply voltage and/or the load condition of the RAMs are significantly altered, the reference voltage is rapidly adjusted by dynamic switching FETs, being pulled down or up. Under balanced conditions when essentially no current flows in the switching FETs, overall power consumption is low.

Reference voltage generator for dynamic random access memory

A digital to analog converter comprising a differential amplifier formed of a pair of similar conductivity type field effect transistors, one transistor being connected to a load for driving the load in synchronism with a digital input signal, means for applying a reference voltage to the gate of the second transistor, and a third field effect transistor of conductivity type complementary to said one transistor, connected with its source-drain circuit in series with the source-drain circuit of the second transistor to a second reference voltage, and means for driving the gates of said one and third transistors together with said digital input signal, whereby the first and third transistors are synchronously and oppositely driven to conduct and cut off, thus ensuring substantially no current flow in the second transistor while the first transistor is conducting.

Growing community of inventors

Constance Bay, Canada

Richard S Phillips