Other

Hyperchip Inc.

4198638 Canada Inc.

Profitable Entertainment Products, Inc.

Richard S Norman

David Chamberlain

Sonja Norman

John Haughey

Marcelo De Maria

Sébastien Côté

Carl Langlois

Yves Boudreault

David Chamberlin

Steve Rochon

Yvon Savaria

Yves Blaquiere

Philippe Dauphin

Robin Boivin

Marcelo A R De Maria

Frederick De St Croix

Jean Bélanger

Eyad Saheb

The present invention is primarily directed to cost-effective systems for using large reflective elements that track the sun on two axes to concentrate solar energy onto a receiver that can convert the sun's optical energy to a form usable for extensive displacement of combustion of fossil fuels. The structures of the tracker frame, tracking mechanism and tracker supports are co-optimized with the optical elements and the receiver for high efficiency, low cost, and ease of assembly, making moderate and large-scale implementations cost-competitive with fossil fuels for peak power, and, with suitable storage, for base-load power and dispatchable peaking power in sunny locations. Improvement to small-tracker two-axis systems and one-axis tracking systems that focus in two dimensions are also included, as are improvements in systems for space-based solar power.

Systems for cost-effective concentration and utilization of solar energy

The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Reprogrammable circuit board with alignment-insensitive support for multiple component contact types

A method, apparatus and computer-readable storage medium for regulating packet flow through a device such as a router with a switch fabric. Congestion information, such as statistics on bandwidth utilization, is collected for each of a plurality of queues at an egress stage of the device. Based on the bandwidth utilization statistics, computations are performed to evaluate a 'discard probability' for each queue. This information is transmitted to the ingress stage, either periodically or at other controlled time periods, such as when the discard probability changes significantly. The ingress stage can then proceed with controllable transmission or non-transmission of packets to the switch fabric, depending on the queue for which the packet is destined and also depending on the discard probability for that queue. In this way, congestion can be avoided even before it even has a chance to occur. This leads to improved bandwidth utilization, since packets which are discarded at the ingress stage will not unnecessarily take up other resources in the device.

Method and system for congestion avoidance in packet switching devices

A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.

Fault tolerant cell array architecture

Methods and apparatus for processing a plurality of sets of routing information received from corresponding ones of a plurality of neighbor nodes connectable to a router, the router having a plurality of memory units accessible via separate paths. The method comprises creating a respective plurality of non-identical routing information subsets from each of at least one of the received sets of routing information; accessing the plurality of memory units via the separate access paths; and storing the plurality of non-identical routing information subsets created from a given one of said received sets of routing information in respective ones of the plurality of memory units. By providing a distributed memory architecture for storing routing information, an increase in a router's memory requirements can be met by increasing the number of memory units.

Methods and apparatus for storage and processing of routing information

A communications bus enables communication of data signals in a parallel processing system having a plurality of substantially identical cells, each cell having an access point for transmitting data signals into the communications bus. The communications bus includes a plurality of parallel channels, and at least one channel crossover point associated with each cell. Each crossover point implements a regular change in a channel order of the communications bus, such that each access point is coupled to a channel of the communications bus. Propagation delays are reduced by inserting buffers at regular intervals along the length of each channel. An output buffer at a downstream boundary of each power domain of the system prevents undesired currents due to voltage mismatch. The propagation direction of data signals away from the access point, and propagation of data to an adjacent downstream cell can be controlled to reduce bus traffic and power consumption.

Communications bus for a parallel processing system

The invention provides for the arrangement and management of timing of various domains on a large integrated circuit which introduces a phase offset between clock domains of neighboring cells to create a wavefront clock which propagates through the circuit at the same speed data propagates though the circuit. The cells of the integrated circuit are wavefront clock synchronized in that the phase offset introduced in a particular cell's clock is such that the arrival of a skewed clock and propagation delayed data from that cell's neighbor is synchronized with that particular cell's own clock. Wavefront clock synchronization mitigates at least some of the problems of clock skew and the associated effects of slowing data propagation and reduction of clock frequencies associated with large surface integrated circuits utilizing synchronized clock domains.

Wavefront clock synchronization

A microelectronic complex including a body of semi-conductor material containing an integrated circuit, and a plurality of contact pads on the body for receiving signal conducting members for connection to an external substrate. The contact pads allow signals to be exchanged between the integrated circuit and the external substrate via the signal conducting members. A majority of the contact pads are disposed on the body of the microelectronic complex according to a configuration whereby the stress effects on the signal conducting members caused by thermal expansion mismatch between the microelectronic complex and the external substrate are minimized. In a specific configuration, a majority of the contact pads form a cluster circumscribing a predetermined area of the microelectronic complex body, whereby the cluster is characterized by a minimum inter-pad distance among the majority of contact pads on the body of the microelectronic complex.

Microelectronic complex having clustered conductive members

A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells. Each cell communicates with at least one other cell of the array, thereby permitting an exchange of data packets to take place between the cells of the array. Each cell includes a memory for receiving a data packet from another cell of the array as well as a control entity to control release of a data packet toward a selected destination cell of the array at least in part on a basis of a degree of occupancy of the memory in the destination cell. In this way, scheduling is distributed amongst the cells of the switch fabric.

Cell-based switch fabric with distributed scheduling

A method and system for regulating packet flow to a downstream entity capable of forwarding packets to a plurality of intermediate destinations. The method includes maintaining a database of queues, each queue in the database being associated with packets intended to be forwarded to a corresponding one of a plurality of final destinations via a corresponding one of the intermediate destinations. Each queue in the database is further associated with a state that is either active or inactive. Upon receipt of a message from the downstream entity indicating a reduced (increased) ability of a particular one of the intermediate destinations to accept packets intended to be forwarded to a particular one of the final destinations, the method provides for rendering inactive (active) the state of the queue associated with packets intended to be forwarded to the particular final destination via the particular intermediate destination.

Congestion management for packet routers

A router includes a routing layer and a switching layer. The routing layer includes a plurality of I/O ports for exchanging data with components external to the router. The switching layer is adapted to switch data packets between I/O ports of the routing layer. The switching layer includes an array of cells in communication with the routing layer for permitting exchange of data packets between the array of cells and the routing layer. Each cell includes a memory for receiving a data packet from the routing layer. The routing layer includes a controller to control release of a data packet toward a cell of the array at least in part on a basis of a degree of occupancy of the memory in the cell.

Cell-based switch fabric with cell-to-line-card control for regulating injection of packets

A connector including a first set of signal conducting members realized at least in part on a first surface and a second set of signal conducting members realized at least in part on a second surface, the second set being remote from the first set. In each set, the signal conducting members are arranged generally side by side. The connector also includes a plurality of connection paths, characterized by a layout for interconnecting the first and second sets of discrete signal conducting members such that signals may be exchanged between signal conducting members of the first and second sets. Specific to the invention, each signal conducting member of the first set is provided with connection paths to a different pair of non-contiguous signal conducting members of the second set.

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Sutton, Canada

Richard S Norman