Novellus Systems Incorporated

Richard S Hill

Steven T Mayer

Willibrordus Gerardus Maria Van Den Hoek

Avishai Kepten

Jonathan David Reid

John Stephen Drewery

Raashina Humayun

Nerissa Sue Draeger

Gary William Ray

Timothy Mark Archer

Jianing Sun

Robert H Havemann

Seshasayee Varadarajan

David Charles Smith

Evan E Patton

Eric G Webb

Gary B Lind

R Marshall Stowell

Mark L Rea

Dinesh S Kalakkad

Bart Jan Van Schravendijk

Bryan L Buckalew

Kaihan Abidi Ashtiani

Karl B Levy

Frederick Dean Wilmot

Larry D Hartsough

Harald Te Nijenhuis

Robert Martinson

Marshall Stowell

Wilbert G Van Den Hoek

Johanes H Sukamto

Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.

Selective electrochemical accelerator removal

Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Topography reduction and control by selective accelerator removal

In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO) or aluminum oxide (AlO).

Protective layer to enable damage free gap fill

Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.

VLSI fabrication processes for introducing pores into dielectric materials

Sonic radiation is applied to a wafer portion of the planar surface of a rotating, tilted wafer as it is being immersed into a liquid treatment bath. The portion includes the leading outer edge region of the wafer. The area of the wafer portion is significantly less than the total surface area of the planar wafer surface. Power density is minimized. As a result, bubbles are removed from the wafer surface and cavitation in the liquid bath is avoided. In some embodiments, the liquid bath is de-gassed to inhibit bubble formation.

Sonic irradiation during wafer immersion

The orientation of a wafer with respect to the surface of an electrolyte is controlled during an electroplating process. The wafer is delivered to an electrolyte bath along a trajectory normal to the surface of the electrolyte. Along this trajectory, the wafer is angled before entry into the electrolyte for angled immersion. A wafer can be plated in an angled orientation or not, depending on what is optimal for a given situation. Also, in some designs, the wafer's orientation can be adjusted actively during immersion or during electroplating, providing flexibility in various electroplating scenarios.

Methods and apparatus for controlled-angle wafer positioning

Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a pre-formed layer of semiconductor to produce a porous semiconductor layer.

Method of fabricating low dielectric constant dielectric films

Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a preformed layer of semiconductor to produce a porous semiconductor layer.

An apparatus and method for controlling and optimizing a non-planar target shape of a sputtering magnetron system are employed to minimize the redeposition of the sputtered material and optimize target erosion. The methodology is based on the integration of sputtered material from each point of the target according to its solid angle view of the rest of the target. The prospective target's geometry is optimized by analytically comparing and evaluating the methodology's results of one target geometry against that of another geometry, or by simply altering the first geometry and recalculating and comparing the results of the first geometry against the altered geometry. The target geometries may be of many different shapes including trapezoidal, cylindrical, parabolic, and elliptical, depending upon the optimum process parameters desired. A sputtering system is developed using this methodology, having a main magnet stack, a rotating magnet, a target having selected target shapes optimized for controlling erosion, downstream magnets, a substrate, and an electric field induced plasma stream.

Control of erosion profile and process characteristics in magnetron sputtering by geometrical shaping of the sputtering target

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Atherton, CA, United States of America

Richard S Hill