Allen-bradley Company, LLC

Rockwell Automation Technologies Incorporated

Richard S Gunsaulus

Otomar S Schmidt

Ronald Edwin Schultz

Charles Martin Rischar

William Edward Floro

Jeffery W Brooks

Gerald S Pepera

Jeffrey W Brooks

A system and method is provided for selecting a test load and/or bias resistor utilized in an expandable load system employing a backup power source. The test load and/or bias resistor is selected based on the actual load present in the expandable system. The backup power source is periodically tested during normal operation of the expandable load system utilizing the test load. A test load is provided that is sized for the actual load of a local load under worse case conditions. If an expansion load is connected to the local load the test load is adjusted, so that the test load is based on the actual load of the local load and the expansion load. Additionally, a bias resistance can be provided for driving a switch that allows power to be provided to the local load during power loss mode. If an expansion load is connected to the local load, the bias resistance is adjusted to correspond to a bias resistance necessary to provide the current for the actual load of the local load and the expansion load.

Self-programmable battery load/bias for memory expansion module

An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.

Integrated relay ladder language, reduced instruction set computer

A memory system uses standard memory devices not normally supporting parity bits. Parity bits for multiple memory devices are stored in a dedicated parity device shared among multiple memory devices. Inadvertent erasure of the parity information, when writing to a single memory device, is prevented by a prereading of the parity device prior to a writing to the single memory device. Special circuitry stores the preread parity information and merges it back with the calculated parity bit for the written data to preserve complete parity information.

Computer memory system providing parity with standard non-parity memory

A co-processor interface allows both a general processor and a relay ladder processor to make repeated calls to each other in the execution of subroutines. A register transfer instruction detected by the relay ladder processor triggers a suspension of the general processor. Return of control to the general processor is accomplished at the same time a register value is provided to the general processor that the general processor uses to reinitialize its program counter. For most single level transfers of control, a single transition instruction between the general processor to the relay ladder processor is sufficient to perform a call.

Bi-directional co-processor interface

A multi-tasking industrial controller for real-time control of machinery and the like permits the use of both periodic and event driven tasks by establishing a hierarchy of both task types in the form of priorities that resolve conflicts between events of the same and different types. Each task may access a common 'global' memory area to communicate information and timing with other tasks and so as to coordinate the overall industrial control process. Trouble-shooting of the task software is made possible by a hardware address monitor which may be programmed to identify access of a particular memory location or range by any task and to record information about the particular task causing that global memory access.

Program analysis circuitry for multi-tasking industrial controller

A method and a circuit limit access to a locked portion of memory to periods when application program instructions in the locked portion of memory are being executed. An UNLOCK routine of processor instructions is executed before accessing the portion of the memory storing the application program instructions and a LOCK routine of processor instructions is executed to re-secure the memory after such access. The locking and unlocking is accomplished by addressing a comparator and transmitting data representing either a lock value or an unlock value. The comparator is connected to enable and disable decoding circuitry which in turn controls access to the locked portion of memory.

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Highland Heights, OH, United States of America

Richard S Gunsaulus