International Business Machines Corporation

Richard S Crouse

Marco M Hurtado

Jose L Rivero

Kha D Nguyen

John J Cazzolla

Luke L Chang

Jose J Ruiz

Louis Salcedo

John J Cazzolla, Jr

Randall P Boudreaux

A system and method is provided for dequeuing connection requests in a data communications system comprising a calling subsystem and a called subsystem connected by a serial simplex switch. The connection requests are made by the calling subsystem to the called subsystem by sending a connect request message to the switch and queuing the connect request message in a buffer therein. The switch establishes a connection between the calling subsystem and the called subsystem by thereafter queuing the connect request message in a buffer in the called subsystem. Concurrently, the switch sends a connect request acknowledge message to the calling subsystem while the calling subsystem sends a connect request dequeue message to the switch. To prevent loss of synchronization between the calling subsystem and the switch, the connect request dequeue message received by the switch is interpreted as a disconnect request message and the connect request acknowledge message received by the calling subsystem is interpreted as a connect request dequeue acknowledge message. The connect request dequeue message and the disconnect request message are identically serially encoded, as are the connect request acknowledge message and the connect request dequeue acknowledge message, to enable such interpretation.

Method and system for dequeuing connection requests in a simplex switch

A sequencing scheme is provided for prioritizing bus operations occurring in simplex switches which interconnect subsystems in a data communications system, thereby yielding improved aggregate system data throughput. The sequencing scheme provides procedures which simultaneously accommodate (i) concurrently pending requests to a first control bus which processes only circuit switched operations and (ii) concurrently pending requests to a second control bus which processes only packet switched operations, in an order which optimizes link level control message throughput of the simplex switch. The control messages which are coordinated by the sequencing scheme include connect and disconnect requests, connect and disconnect request acknowledgments, and data acknowledgments. All connect request and disconnect requests are managed by a connection processing (CP) bus, which operates as a circuit switching bus, and all data acknowledgments and connect request acknowledgments from subsystems attached to a cascaded switch are made over an out-of-band (OB) bus, which operates as a packet switching bus. Because connect and disconnect operations over the CP bus can proceed independently of acknowledgment operations over the OB bus, the sequencing procedures for each of the control buses are permitted to operate independently and simultaneously.

Method of sequencing bus operations in a simplex switch

A serial simplex switch design is provided which includes I/O ports each of which is configurable specifically for attachment to a data communications subsystem or, alternatively, for cascaded connection to a similarly configured I/O port on another switch. The switch provides a packet routing function including input and output buffers for each of its I/O ports wherein packets of control messages sent by one subsystem are temporarily stored prior to being delivered to the appropriate destination subsystem. When configured to be directly attached to a subsystem, the I/O ports separate control messages from incoming integrated data and control message strings. In a cascade configuration, however, a mechanism is provided wherein data and control messages are separated into two physical paths to eliminate the delays associated with integrated data and control message flow through the cascaded I/O port. Each I/O port is configurable to either of these methods of operation by means of programmable latches associated with the I/O port.

High performance cascadable simplex switch

A method of operating a digital data processor includes the supplying to the digital data processor of a branch and return on address (BAROA) instruction having an operation code field, a memory entry address field and a memory exit address field. This method also includes for such branch and return on address instruction the steps of loading the operation code field into an instruction register, loading the memory exit address field into an address register and loading the memory entry address field into a program counter. This method further includes storing the next sequential address following the address of the current BAROA instruction into a register stack, and then fetching from memory and executing a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction. The program counter is incremented each time an instruction is executed. In this manner, the program counter provides the memory addresses of the instructions to be fetched. This method further includes the steps of comparing the memory address in the program counter with the exit address in the address register and loading a return instruction operation code into the instruction register when the memory address in the program counter becomes equal to the exit address in the address register, such return instruction operation code, in turn, causing the address stored in the register stack to be loaded into the program counter.

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Boca Raton, FL, United States of America

Richard S Crouse