Zing Semiconductor Corporation

Enraytek Optoelectronics Co., Ltd.

Sien (qingdao) Integrated Circuits Co., Ltd

Richard Rugin Chang

Deyuan Xiao

Mengjan Cherng

Qing Rao

Chijen Hsu

This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a subtract; a P-type semiconductor channel and an N-type semiconductor channel, suspended on the subtract; a gate dielectric layer, wrapped around the P-type semiconductor channel and the N-type semiconductor channel; a gate electrode layer, wrapped around the gate dielectric layer; a P-type source region and a P-type drain region, connected to two ends of the P-type semiconductor channel respectively; an N-type source region and an N-type drain region, connected to two ends of the N-type semiconductor channel respectively; wherein the doping concentration at the surface of the P-type semiconductor channel is the highest, then decreases from the surface to the center region, the doping concentration at the surface of the N-type semiconductor channel is the highest, then decreases from the surface to the center region, and a cross-sectional width of the P-type semiconductor channel is greater than that of the N-type semiconductor channel. The present invention has ability to realize multi-layer staking under unit area, and reducing the length of the channel effectively so as to reduce channel effect and improve carrying capacity and integration level of the device.

Nanosheet CMOS semiconductor device and the method of manufacturing the same

This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.

SOI substrate and manufacturing method thereof

This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

Method for growing monocrystalline silicon and monocrystalline silicon ingot prepared thereof

This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, the silicon-containing materials comprising a deuterium-implanted nitride-deposited silicon and a monocrystalline silicon, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

Method for making III-V nanowire quantum well transistor

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

Thermal processing method for wafer

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

A method for making III-V-on-insulator on large-area Si Substrate wafer by confined epitaxial lateral overgrowth (CELO) has been disclosed. This method, based on selective epitaxy, starting from defining an epitaxy seed window to the Si substrate in a thermal oxide, from which the III-V material will grow.

Method of preparation of III-V compound layer on large area Si insulating substrate

A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.

Fabrication method for forming vertical transistor on hemispherical or polygonal patterned semiconductor substrate

The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. The width of energy band gap of the barrier layer is wider than that of the channel layer. Thus the two dimensional electron gas (2-DEG) generated in the interface between the channel layer and the barrier layer of this junctionless field effect device has higher electron mobility. The structure of the device of this disclosure has a higher breakdown voltage which is advantageous for a high voltage junctionless field device. The structure offers advantages in device performance and reliability.

High voltage junctionless field effect device and its method of fabrication

A lighting circuit comprises a first rectifying diode (D), a second rectifying diode (D), a third rectifying diode (D), a fourth rectifying diode (D), a first group of LEDs (LED, . . . , LED), a second group of LEDs (LED, . . . , LED), a third group of LEDs (LED, . . . , LED), and a fourth group of LEDs (LED, . . . , LED). The first group of LEDs (LED, . . . , LED) is connected between the anode and the cathode of the first rectifying diode (D); the second group of LEDs (LED, . . . , LED) is connected between the anode and the cathode of the second rectifying diode (D); the third group of LEDs (LED, . . . , LED) is connected between the anode and the cathode of the third rectifying diode (D); the fourth group of LEDs (LED, . . . , LED) is connected between the anode and the cathode of the fourth rectifying diode (D).

Lighting circuit

An LED includes a first electrode, for connecting the LED to a negative electrode of a power supply and a substrate located on the first electrode in which a plurality of contact holes are formed extending through the substrate. The diameter of upper parts of the contact holes is less than the diameter of lower parts of the contact holes, and the contact holes are filled with electrode plugs connecting the first electrode to the LED die. The light emitting device includes the LED, and further includes a susceptor and an LED mounted on the susceptor. The manufacturing method includes forming successively an LED die and a second electrode on a substrate, patterning a back surface of the substrate to form inverted trapezoidal contact holes which expose the LED die, and filling the contact holes with conductive material until the back face of the substrate is covered by the conductive material.

Light emitting diode and a manufacturing method thereof, a light emitting device

A light emitting diode (LED) and a forming method thereof are provided. The LED includes a semiconductor substrate, a bonding layer formed on a surface of the semiconductor substrate, and a LED die formed on a surface of the bonding layer. The effective lighting area of the LED may be increased, heat radiation may be improved, and lighting efficiency may be enhanced.

Light emitting diode and forming method thereof

A light emitting diode (LED) and a forming method thereof are provided. The method for forming the LED includes: providing a semiconductor substrate () and a sapphire substrate () respectively, wherein a first bonding layer () is formed on the silicon substrate (), and a sacrificial layer (), an LED die () and a second bonding layer () are formed in turn on the sapphire substrate (); bonding the first bonding layer () and the second bonding layer (); removing the sacrificial layer () and lifting off the sapphire substrate (). The method increases the effective lighting area of the LED, improves heat radiation, and enhances lighting efficiency.

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Shanghai, China

Richard Rugin Chang