Intel Corporation

Richard Reohr

Jie Ni

Kevin B Stanton

Briefly, in accordance with one embodiment of the invention, an apparatus includes an integrated circuit that has the capability to schedule transferring processes that have an individual identification number. At least a portion of each individual identification number is used to indicate the presence of each of the transfer processes. Briefly, in accordance with another embodiment of the invention, an integrated circuit having a scheduler of transfer processes, each of the transfer processes having an identification number. The scheduler is coupled to a memory array of bits, and a portion of each identification number is used as a portion of an address to the memory array of bits. Briefly, in accordance with yet another embodiment of the invention, a method of scheduling requests for the transfer of data where each request having an identification number. The identification number is used in addressing a bit in an array of bits and set to indicate the request for the transfer of data.

Method and apparatus for scheduler coupled to memory array wherein scheduler addresses array with at least a portion of an identification number

A method and apparatus are presented for implementing the next-address determination within a binary search algorithm. A binary search algorithm searches for a compared within a one dimensional sorted array of elements. Typically, a binary search algorithm comprises a comparator and a next address generator. The next address generator determines the address of the next array element (the &ldquo;next address&rdquo;) a comparator will search using both a &ldquo;compared is greater&rdquo; signal from the comparator and a signal which indicates the address of the last array the comparator searched (the &ldquo;previous address&rdquo;). The time needed to search an array for a compared inserts a delay in applications where a binary search algorithm is employed. One method of expediting the searching process is to minimize the number of gates between the input and output of the next address generator (the &ldquo;critical path&rdquo;). In an embodiment of the present invention, two gate levels are used within the critical path to increase the rate at which a search can be performed even when the search is interrupted and resumed after performing some other task.

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Hillsboro, OR, United States of America

Richard Reohr